12-31-2021 04:47 PM
Thank you for your answer. NI FPGA derived clock gives the capacity to produce 800 mhz, how is this possible. Is there a possibility to create this frequency?
Another thing I'm wondering is that if I divide the loop into two, I get 10 MHz output. If I divide it by 3, I get an output of 6.666 MHz. Is there a way to elaborate on this?
I want to produce more detailed frequencies between 10KHz and 5MHz. For example, if I want to produce 4.5Mhz-4.4Mhz, what can I do?
12-31-2021 05:00 PM
Have you made a software version of what you want to generate?
Sorry if you have posted it already.
This could help greatly.
Regarding clocks, the single cycle timed loop is not configurable at runtime so it must remain fixed. Variations have to happen via logic as mentioned earlier.
01-01-2022 08:16 AM
This issue has been resolved. Thanks for all the help.
01-05-2022 02:55 PM
Sorry, the code is attached.I thought it wasn't necessary.What I want to do here is to use DIO pins on both FPGA and Myrio.
05-19-2022 11:34 AM
In NI-FPGA, there is 40MH speed. One loop will take one tick. SO wait for 4 tick that could generate 10Mhz pulls.