Labview NI-FPGA, generating N pulses at high frequency (1-5 MHz)

[Bob_Schor]

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@constructionworker wrote:

-When any number is entered, that number of pulses should be generated and sent at the determined frequency.
-If the number of steps is changed before the number of given steps is over, and if the number of steps is less than the number of steps given before, the stepping is stopped. If the number of changed steps is still greater than the number of steps taken, it reaches the number of new steps and stops, waiting for new steps.

I need to be able to create a frequency between 1-5Mhz and the frequency needs to be changed instantly.

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I believe the logic I described could be modified to handle the changes you mentioned, though adding quite a bit of complication (and the possiblity/probability of error during execution because of race conditions) to the code.  I also worry when I hear "frequency needs to be changed instantly" because this unavoidably introduces high-frequency "transients" (though these also are present when you "instantaeously" start and stop a signal without tapering its amplitude).

Bob Schor

[constructionworker]

Thank you for your answer.GerdW
But in the example you show, only 500 khz frequency can be produced.

The picture in the previous post was a test I wanted to adapt to the FPGA code.
Now I have the problem of DIVIDE I created.VI is as below

[GerdW · Accepted solution]

Hi worker,

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@constructionworker wrote:

Thank you for your answer.GerdW
But in the example you show, only 500 khz frequency can be produced.

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Wrong.

As mentioned several times you need to change the wait function to wait for clock cycles instead of µs…

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@constructionworker wrote:

The picture in the previous post was a test I wanted to adapt to the FPGA code.
Now I have the problem of DIVIDE I created.VI is as below

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Again you attached a FPGA VI without context - did I asked for the lvproj file before? That lvproj file contains all the definitions for your RT/FPGA target including the 5MHz clock used for this SCTL…

Why do you need to divide in the FPGA? Why do you need to divide integer values?

Two suggestions:

• When you REALLY need to divide in the FPGA VI then you should use FXP values.
• I recommend to offload ay divisions to your RT host: it can easily provide all configuration data for your FPGA VI…

Please cleanup the VI for left-to-right dataflow.

Why don't you initialize the shift registers?

[constructionworker]

Thanks a lot for the reply.

I thought it might be unnecessary to include the lvproj file. Sorry. Next time I will also add the Lvproj file.
The reason why I want to split the FPGA; Instead of creating a frequency of 40 MHz, I wanted to make instant changes between 0-hz-5 MHz. But I was not completely successful. I realized that I need to use FXP.
After the example you gave, I think I'm going to make a lot of changes to the code, I'll still have to clean it up.

- When any number is entered, that number of pulses should be generated and sent at the specified frequency. -If the number of steps is changed before the given number of steps is finished and the number of steps is less than the number of steps given before, the step is stopped. If the number of changed steps is still more than the number of steps taken, it reaches the new step number and stops, waiting for new steps.

One more question, why can a maximum frequency of 5MHz be generated in the example you gave? Do I need to create an SCTL to generate higher frequencies?

[GerdW]

Hi worker,

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@constructionworker wrote:

One more question, why can a maximum frequency of 5MHz be generated in the example you gave? Do I need to create an SCTL to generate higher frequencies?

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My example will give the option to run the loop at 5MHz because the FPGA is fast enough to provide that iteration speed…

Keep in mind: code in the FPGA is equivalent to hardware, it is not bound by any resource occupation/CPU load after compilation!

The SCTL allows to execute the code within the loop in exactly one cylce of the clock used to time that SCTL. When you use a 40MHz clock for a SCTL it will allow you to iterate at 40MHz…

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@constructionworker wrote:

When any number is entered, that number of pulses should be generated and sent at the specified frequency.

If the number of steps is changed before the given number of steps is finished and the number of steps is less than the number of steps given before, the step is stopped. If the number of changed steps is still more than the number of steps taken, it reaches the new step number and stops, waiting for new steps.

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These are new requirements: you should have given them right in the beginning of this thread…

(How many pulses do you want to generate at 1MHz and how fast/often do you need to change the number of pulses while generating them?)

[constructionworker]

It needs to detect the pulse change momentarily.

I'll adapt the piece of code I want to generate and get back to you with the code I've created. I don't want to bother you like this anymore. If you can tell me what I'm missing, that's enough.thank you very much.

There's a lot I don't know about the NI-myrio FPGA. But I want to ask a few questions. There are a few things I'm wondering about.
How does the piece of code I use in the NI-FPGA affect the code I create in Myrio?
-How many frequencies can be produced with NI-FPGA?

Thanks for all the answers.

[GerdW]

Hi worker,

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@constructionworker wrote:

How does the piece of code I use in the NI-FPGA affect the code I create in Myrio?

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It does not "affect" the code of the myRIO host, but the FPGA VI can interact with the RT host VI.

(This is explained in all those example projects for RIO devices…)

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@constructionworker wrote:

How many frequencies can be produced with NI-FPGA?

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All you need…

The FPGA runs on a 40MHz clock, so one cycle takes 25ns. You can generate each frequency where 40MHz is a multiple of (like 20MHz, 5MHz, 1.25MHz, 10kHz,…)!

You might even try to use derived clocks, but AFAIK the DIO pins of the myRIO allow upto 40MHz update rates…

[constructionworker]

thanks for the answer.

I wrote a code as attached.
This code does exactly what I want. But I have a question.

Currently, I can generate 20 MHz using SCTL. I think the reason why 40MHz cannot be generated is because of the code I created. Not that it's necessary at the moment, but I was still wondering. If I want to make the MHz frequencies more precise. How can I do that. Currently I generate a maximum frequency of 20MHz. If I divide the while loop 2 into two, 10 MHz frequency can be created. If I want to change the frequency in more detail (example as: 19.25MHz) what can I do. Or is there an obstacle to doing this?

[Bob_Schor]

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@constructionworker wrote:

Currently, I can generate 20 MHz using SCTL. I think the reason why 40MHz cannot be generated is because of the code I created.

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No, the reason you cannot generate 40 MHz is (as GerdW explained) the FPGA, itself, runs at 40 MHz, which means it can make a change (say, from High to Low) in 1/40,000,000 = 25 ns.  To make a "cycle", you need to "cycle", i.e. go from Low to High to Low (or from High to Low to High), which takes 2 x 25 ns = 50 ns.  Something that changes every 50 ns has a frequency of 1/50 GHz = 20 MHz.  Time is "quantized" in the FPGA, and the quantum of time is 25 ns.

Bob Schor

[Terry_ALE]

FPGAs have clock managers which can derive many different clocks higher and lower than 40 MHz

Direct Digital Synthesis is how FPGAs can generate various clock types on the fly.  The https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpga/sine_generator/ function likely has this behind the scenes.  The frequency shift  function can also be used to generate varying signals in the FPGA as well.