LabVIEW FPGA: Integration Node Clock Trouble

[Akello]

Hello,

I am having some trouble understanding how the clock fits in with the IP Node for LabVIEW FPGA and was hoping to get some advice.

What I am trying to do is implement a digital logic circuit that has an 8 bit MUX feeding a parrallel shift register. I created the schematic for this in Xilinx ISE 12.4, implemented and am able to import the HDL code into an IP Node. When I run the VI, I am able to select between the two inputs for the MUX, load the output into the shift register, clear the shift register and activate the CE.

My problem is that when I toggle the CE input, it should begin shifting 1s (Boolean Trues, VCC, High, what-have-you) into the register once every clock period. Unfortunately it makes all 8 bits 1s instantly. I suspect this is a clock issue and below are some of the things I tried:

-Specifying the clock input while going through the IP Node Configuration process.

-Adding an FPGA Clock Constant as an input to the timed loop.

-Removing the Timed Loop and just specifying the clock input (I am not able to run the VI as I get an error that calls for a Timed Loop)

-Not specifying the clock input in the IP Node Configuration and wiring the FPGA Clock Constant to the clock input (I can't because the input is generated as a boolean).

-Removing an earlier version of the CE that had two inputs going to an AND gate in ISE.

-Specifying the CE in the IP Node Configuration process.

-Not specifying CE in the IP Node Configuration process and wiring it sperately.

-Various reconfigurations of the same that I can't recall.

I think I am doing something wrong with the clock and that is the problem I am having. Previously, when I posed questions on the board about importing ISE code into LabVIEW FPGA, a clock signal was not required and I was advised to just used a timed loop. Now I need to use it but am unable to find an explanation online, especially as it concerns an IP Node.

Any advice would be greatly appreciated as I am working on a project that will require an understanding of how clocks fit in to the IP Node.

Thanks in advance,

Yusif Nurizade

P.S. I've attached my ISE schematic and LabVIEW project with one of the incarnations of the VI. The site won't allow me to add a .vhd file as an attachment but if it would help I could just paste the body of the VDHL code so just let me know.

[REDS]

Hello Akello,

Thanks for posting your attachments and the troubleshooting you have followed. Can you clarify to me what the CE is? Is it chip enable? If so, then I wouldn’t expect that you would shift the Boolean values on the shift register with that, as the MUX’s chip enable would just put the MUX in high impedance and no value would be available at its output.

Is it clock enable? Did you write your own IP? If so, I think that this link could help you. You actually need to specify the ports that correspond to your clock enable. Have you tried to follow the configuration wizard as shown on the help document?

[Akello]

Daniel,

Thank you for your response. I was starting to worry that posting this question around the holidays was a bad idea.

To answer your question, CE is the clock enable. I did not write my own code; it was HDL generated from a schematic I made in Xilinx ISE. The schematic is a simple digital logic circuit and synthesizes without issue in Xilinx. I did follow the Wizard in specifying the inputs including clock, enable, clear, etc. and was able to run the VI. In fact, everything but the Clock Enable works fine; I can toggle between inputs, load them to the register and clear without issue. My problem occurs when I toggle the CE and all the inputs become High/1/True simultaneously. 

My professor, one of the the NI Engineers I spoke to when I called in about my issue and I suspect the problem to be an issue of clock speed. The slowest clock frequency I can get out of the FPGA clock is something like 3.125MHz which would cause the shifting in of High/1/True values to appear almost instaneous and could very well explain the problem.

If this is in fact the issue, however, I am at a loss for how to slow the clock speed down enough to verify the functionaility of the CE and by extension the digital logic circuit I created. The NI Engineer I spoke to suggested not listing the clock input in the Configuration Wizard. This causes the clock input to appear as a boolean input in my IP Node and the NI Engineer's suggestion was to toggle it manually allowing me to control the clock speed. When I do this, however, nothing works including Load and CE. 

Xilinx, by comparison, has an option that allows you to zoom in on the clock speed in the simulation and view something that is going on in a fraction of a second. My question is how I can do the same with LabVIEW FPGA since my project requires using IP Nodes with a clock input and if everything can only happen in real time, it would be almost impossible to troubleshoot.

I know this is a pretty specific topic but there really is no relavant literature or posts that I could find online.

Any help is greatly appreciated,

Yusif Nurizade

[REDS · Accepted solution]

Hello Akello,

I talked to the NI Engineer about this and it seems to be that in order to verify that your code works, it sufficed by putting a 500 ms Wait function on the While loop to verify that the registers get loaded and clear. I'm glad that this worked out fine!

[Akello]

Daniel,

The solution in fact works brilliantly. If I place a 1000ms (1sec) wait on the outer while loop, the code VI executes perfectly and I am able to see the high values shifting in.

Thanks so much for your help, hopefully whoever else encounters this problem will now be able to find the solution quickly.

Yusif Nurizade