LabVIEW Bug When Sharing Module Timebases?

[mbremer]

I seem to have found a bug in LabVIEW when configuring an external timebase source for a module.  It seems that when I choose a different timebase for a module (exported from another module) LabVIEW stops unloading properly when closing VIs and project files.  Everything seems to stay in memory, so when I open a VI and then close the project, the VI remains open.  Re-opening the project pops open the project explorer windows very quickly as if the project wasn't actually unloaded and the explorer window was just closed.  It doesn't seem to unload VIs and projects from memory until I close LabVIEW.  On;y then will it ask if I want to save VIs that were loaded during the session (and not yet saved).

Can anyone else confirm this behaviour? I've replicated in LabVIEW 2018 and 2017 and have attached the files for both.

[mbremer]

Another curious development.  I opened an older project and was seeing the same behaviour.  I don't do any external timebase configuration though.  I replicated in a simple project by just adding a single module to the FPGA target (see attached).  I've tried a number of other modules and it seems to only happen with the NI 9775 module and the third-party PROFINET module from Kunbus.

Here's another strange wrinkle though.  I recently switched to a new laptop and never had this problem when working on this project on it.  This makes me think that it's something with my environment.  Another coworker sees the same issue, but he has the same type of laptop as I do.  Also, I can't replicate the issue in a VM that I have.

Anyone have any ideas?

[MichaelS78]

If I add 3rd party Wireflow 3168 modules to my RT target  I have the same issue. - namely closing the project leaves VI's open.  Is there a workaround yet?  I frequently have to use task manager to get LabVIEW to close the 'getting started' window.  I close the project, VI's stay open.  I close all of the VI's.  The getting started window does not open but it is showing as a taskbar icon, so its process is open but it is hidden.  Then I have to kill LabVIEW with task manager.

I am using LabVIEW 2018 SP1

[benjamin-hinrichs]

I can confirm the behaviour in LV2018 SP1 as well as a freshly installed LV2020 32bit.

I changed your project file (add a build spec) without saving and then closed it. The save dialog then offers to "Defer Decision", which means it'll remain in the background. When closing the LabVIEW startup screen, finally it'll ask to save the project I already closed. Could also show the project was still open using LAVAG LabVIEW Task Manager. 

Since I'm having problems deploying to cRIO target (could be unrelated to this issue), I will keep my FPGA configuration and programming in a separate project and load only the bitfile in the RT project.

Thanks!

[James_McN]

This sounds a lot like a similar problem being reported in https://lavag.org/topic/21687-lv2020-project-save-weirdness/?tab=comments#comment-132945