How to import Verilog codes into LabVIEW FPGA?

[softmind]

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3, 

but still I can see some errors while compiling the VI file.

Simple test Verilog file is as follows:

==============================

module andtwobits (xx, yy, zz);

input xx, yy;
output reg zz;

always @(xx,yy) begin
zz <= xx & yy;
end
endmodule

==============================

and after following up the above link, we created the instantiation file as

==============================================

library ieee;
use ieee.std_logic_1164.all;

entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
);
end mainVHDL;

architecture mainVHDL1 of mainVHDL is

COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;

begin

alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);

end mainVHDL1;

==============================================

Sometimes, we observe the following error when we put the indicator on the output port,

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =

TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.

and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.

Could you take a look at and please help me to import Verilog to LabVIEW FPGA?

I've followed the basic steps of instantiation on the above link, but still it won't work.

Please find the attachment for the all files.

- andtwobits.v : original Verilog file

- andtwobits.ngc: NGC file

- andtwobits.vhd: VHD file after post-translate simulation model

- mainVHDL.vhd: instantiation main file

Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.

Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.

Bests,

[Wee-Bey]

Hi softmind,

You say that this error occurs just sometimes when the indicator is hooked up to the output port? So does it work some other times?

If so, what kind of environmental differences are there when it works versus not working? 

What version of LabVIEW, LabVIEW FPGA, and Xilinx ISE are you using? We have had errors in the past where older versions of some of this software cause similar errors.

[softmind]

Hi Wee-Bey,

You can check the attached files for the better understanding.

When there are only controls in the VI (input ToCLIP), it does not give any error, but once I put the indicator in the VI (output FromCLIP), it will show the error.

I think that it does not execute or include the Verilog properly when there is no indicator (CLIP output), so it is the reason why it does not show any error, but once I put the output, then LabVIEW should execute the CLIP, so it may give errors.

I tested two kinds of versions,

- LabVIEW 2011 with Xilinx ISE 12.4 (I used the one in the NIFPGA folder (installed when I install Xilinx Tools)

- LabVIEW 2012 with Xilinx ISE 13.4 (from NIFPGA)

So, I don't think it was not the problem of older versions

[Wee-Bey]

softmind,

You might be right about the CLIP not executing until there is an indicator there.

The KnowledgeBase you referred to states in Step 2 that you cannot use the latest versions of ISE (11.1 or later) to build the wrapper. 

The following links lead to ISE 10.1 for LabVIEW 2012 and 2011, which you can use to adhere to those guidelines.

LabVIEW 2012 FPGA Module Xilinx Tools 10.1

LabVIEW 2011 FPGA Module Xilinx Tools 10.1

[softmind]

Thank you very much for your suggestion.

Based on your recommendation, we installed Xilinx Tools 10.1 version, and tested the same thing using that ISE.

But, the problem is not resolved even though we used the lower version of Xilinx Tool.

I can find the example to import VHDL codes into CLIP from the following link:

http://www.ni.com/white-paper/7444/en

and I'm very pleased if you and/or NI people can give any kind of very simple example code to import VERILOG into CLIP.

Since there is no specific example to import VERILOG code, 

I guess that the example is worthwhile as a benchmark for the customers 

because the customer can test their own environments using test code and figure out the problems and solutions by themselves.

Please help me for the verilog instantiation part, and if it is hard to make, and please recycle the example I uploaded to the forum and give some idea what parts should be polished for the Verilog Import.

I'm really looking forward to getting any help. 

Thank you very much for all supports from NI.