11-29-2012 10:42 PM
Hi Spex,
Thankyou for your valuable advice in time.I was posting for the first time so could not notice that it was an already solved thread.Well i have re-posted my question on this link http://forums.ni.com/t5/Real-Time-Measurement-and/Compilation-error-in-importing-VHDL-Wrapper-file-f.... Now looking forward to help from other engineers regarding this issue.
Cheers!
03-08-2015 11:27 AM
Hi Softmind,
I also need to import the Verilog file into Labview, but cannot open the link
http://digital.ni.com/public.nsf/allkb/7269557B205
Any help?
Thanks,
03-08-2015 11:30 AM
Hi @T-REX$,
It seems there is manual about how to import the verilog file into Labview. But I cannot open the link you posted, as I cannot open the link Softmind referred to.
Would you kindly send me the file of the hypelink you posted?
Thanks,
@T-REX$ wrote:
The best instructions that we have for integrating Verilog IP into LabVIEW FPGA can be found here: Using Verilog Modules in a Component-Level Design. My suspicion is that you didn't uncheck the "Add I/O Buffers" option in the Xilinx Specific Options setting in ISE when running XST (see page 8 of the .pdf)
03-09-2015 02:00 PM
Try this white paper instead: http://www.ni.com/tutorial/7444/en/
It discusses how to integrate external IP into LabVIEW FPGA.
10-14-2024 01:21 AM
Dear T-REX$,
The page about example is lost. Could you share it again please?
Much thanks.
10-14-2024 01:29 PM
I think this is the same KB: Using Xilinx ISE Design Suite to Prepare Verilog Modules for Integration Into LabVIEW FPGA - NI.
10-14-2024 08:15 PM
Thank you very much. And I wonder if Labview FPGA only supports VHDL to be integrated and not verilog.