LabVIEW
FPGA slew rate settings
Solved!
Hello,
please does somebody tried change "Slew rate" on FPGA I/O pins ?
I have PXIe-7820R which have Kintex-7 FPGA. With google I find Xilinx datasheet, there is written "..designer can specify the slew rate..". I expect FPGA have some registers to control slew rate individually (i.e. I expect something like on STM32 or ARM).
So then how to do it in Labview + RT + FPGA module ?
Because I see only available these thru FPGA Method node.
K.P.
You can do that only on FPGA pins directly when creating a CLIP for the pinout on sbRIO devices. It’s then compiled into the bitfile and in essence is controlled by the amount of current the oupuf driver is allowed to use. High current means high slew rate but also chance of ringing on the output.
What you have is an IO of a module which is NOT an FPGA pin but a module pin and they only support settings that the module supports. And I’m not aware of any module allowing to set the slew rate. It doesn’t make much sense too. Those pins are all much slower than an FPGA pin and the amount you can change it in the FPGA pins would make no difference on that slower speed of module pins.
I do not know FlexRIO though so there may be a way but I would not expect to find it in the method node.
