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FPGA overmapped error: optimization problem



I've been trying to implement a PID loop on a labview FPGA board, and my VI won't compile because it's overmapped (see the link below). I'm trying to trigger the PID loop on an external trigger and read the setpoint from the host VI. It seems like the problem is having a control for the gains on the front panel (since it compiles if I replace the control with a constant), but I tried implementing a FIFO for the PID values and was getting the same error. I'm not sure what I can do to optimize my code. Would someone be able to take a look at the attached code? 




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Hi atirone,


the main problem here is NI's decision to use SGL values for the PID implementation.


Create your own PID function using FXP values. This should free a lot FPGA resources!

Best regards,

using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 2 of 3

What GerdW said.


This white paper by Xilinx shows that it's usually a 5x to 10x improvement moving to FXP.

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