FPGA Max and Min

[guilio_2008]

Attached is a simple code I am trying to do in FPGA.  I am sending a signal to my 9215.  The wave can be sine, triangular, etc....doesn't matter nor does the freq.  What I need is the Max and Min of the signal at each cycle.  The problem with the code is that I get the max and min of each cycle, but when the 0 crossing occurs, the max and min of that previous cycle are reset to 0 rather then just being held until the new max and min of the cycle found.  I would like for the max and min to be held until the new max/min is found, then replaced.  I know why this is occuring, however, I am having difficulty trying to solve this solution.  I tried another case structure, and it does the same thing.  I feel this is a fairly simple problem to be solved and I am probably overlooking the obvious answer.  All help appreciated as well as suggestions.

Thanks,

guilio

[Wiebe@CARYA]

Any reason you don't use the Min Max function (in the comparation palette)?

Avoid cases at all costs on your FPGA. Use a case selector instead.

Regards,

Wiebe.

[guilio_2008]

I didn't use the max and min from the comparison pallet because I need this to get the max and min of each cycle and there wasn't a way for me to reset the max and min to 0.  Also when just plugging in the single input number, I get the same thing of it counting each input rather then just holding the max and min.

Thanks,

guilio

[wiebe@CARYA]

Guilio,

You can still use the min max for the inner case...

If you want to hold the maximum, until a new cycle has a new maximum, you'll need another feedback node. I prefer shift registers. See attached picture.

Regards,

Wiebe.