FPGA I/O

[nwild]

Hi, Can you have two host sub VIs accessing an FPGA at the same time?  I would like to have one host sub VI read several U32 indicators on the FPGA VI front panel while a second host sub VI reads a boolean on the FPGA VI front panel.

My plan would be to wire the reference out of the Open FPGA Reference Function to two instances of the FPGA Read/Write control.

Do I need to synchronize these read operations or can they be asynchronous and possibly occur at the same time?

Thanks,

Neville

[nwild]

Hi, Do you need to guard against two host sub VIs accessing the FPGA at the same time?  I would like to have one host sub VI read several U32 indicators on the FPGA VI while a second host sub VI reads a boolean on the FPGA VI.  Do I need to synchronize these operations or can they be asynchronous and possible occur at the same time.

Thanks,

Neville

[GerdW · Accepted solution]

Hi Neville,

you can access the same FPGA reference in several VIs at the same time!

Edit: Please don't spread the (basically) same question in several threads…