FIFO overflow

[eBuddy]

Dear experts...

My task is to demodulate a signal of 20 MHz which is input to the NI 5781 FPGA module. I am trying to sample the signal at 80MHz rate at FPGA and via FIFO sending data to RT. On RT I am trying to do further processing (Screenshot of FPGA and RT vi attached). Now on RT when i Start program, for a second I get desired output but immediately i receive only noise signal (Screenshot of Expected output and Real output is attached). What I believe is my FIFO is being written much faster than being read. I tried to increase the size of FIFO but still it remains same. For sometime i get proper output and then noise. Is there any solution to overcome this issue. Can I have the timed loop at RT which clock can be exactly as the clock of timed loop on FPGA (80 MHz in this case). I checked timed loop on RT but it is giving only 1 Khz as execution rate.

Thanks... Kindly help...

[nathand · Accepted solution]

On the RT side, read more than one element at a time from the FIFO.  You know what the sample rate is, so read a fixed number of samples with a timeout large enough to receive that number of elements.  Another common approach, especially when the sample rate can vary, is to read 0 elements, which will return the number of elements remaining in the FIFO, then read that number of elements with a shorter timeout since you know that those elements are already available.

[eBuddy]

Thank you very much nathand... got the output