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Error Code 61057 causing compiler freeze

Hello, all who may read this:

I am currently programming a VI to be put onto a PXI-7831R RIO card. It consists of a SCTL that is monitoring the state of a digital pin. The program runs fine when I am emulating it on the PXI-7831R. When I attempt to compile it and actually download it to the card, I get the following error:

Error Code: 61057: Error: Component rvi_Instance_139_11DigitalSLTC must directly connect to an uninitialized shift register.

(Note: DigitalSLTC is VI name)

I am unfamiliar with this error code and also the component instance it is calling, but I tracked it down by removing components and it seems to be an '=' comparator. When that piece is removed, it compiles fine (but of course, does not function as I wish it to).

An equivalent comparator (subtracting values of interest and checking =0) generates the same error. So, my main question is what the error code means; hopefully a better understanding of the error will help me to solve the problem (while continuing to be intentionally vague about the actual code).

Thank you!

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Message 1 of 4

The error that you are receiving is caused by having too many operations in sequence in your SCTL. The number of operations in the SCTL is limited so that the board can maintain the loop rate. You will most likely need to implement pipelining in order to make your code usable in the SCTL. The FPGA User Manual has information regarding running code in parallel so that it can run properly. Refer to the section Executing Code in a Single FPGA Device Clock Cycle on page 2-9.


Danny G
Applications Engineer
National Instruments
Message 2 of 4

Thanks for responding.

I don't believe that pipelining/too many operations is the culprit in this problem. I stripped off every nonessential piece of code and am only running the following SCTL, which contains only a stepthrough of the addresses of the table (see attached jpg). I have also attached the configured table. It only has four values and the linear interpolation function is disabled.

I'm using a look-up 1D table, which I am assuming is compatible with SLTCs. The following link seems to suggest that while FPGA Math and Analysis functions do not work, the Linear Interpolation and 1D Tables do (that bullet is ambiguous though):

Plus, the error is different from one seen when using a VI that is blatantly SCTL incompatible (that one is something like VI_name:238ba9b8bc8d9b78d98dd8b9d7cd is not supported for use in SCTL), so I don't know. Perhaps I have the table set up incorrectly? Am I not indexing the address properly? Are 1D lookup tables not supported, despite the ambiguity on the above link?

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Message 3 of 4

After reading what you suggested, there is a little paragraph that explained how to use uninitialized registers with SCTL memory reads (on pg. 2-11), since the table output is valid only the next time around. Putting the indicator before the memory table (but after it, through a shift register), and it compiled fine.

Thanks very much for the help!

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