08-06-2018 04:01 AM
Just some random thoughts...
Without looking at the code, I think a general 'solution' might be to use extended floats in stead of double floats. I quoted solution, because it will just delay the problem: the resolution is orders of magnitude better, but still limited. Not sure if that will work on an FPGA. I think doubles are supported, don't know if extendeds are.
Another solution (not sure if it applies here) is to store the number of subtractions (as an 64 bit integer) and multiply this with the number to be subtracted. Then subtract that each iteration. That would avoid the cumulative error.
08-06-2018 05:14 AM
I'm pretty sure the SubVI-Truncated-Cusp.vi as posted will not compile on an FPGA.
DBL is not supported on FPGA as far as I know, unless something changed recently, I'm on LabVIEW 2015.
08-06-2018 06:18 AM
Think you're right, probably only singles are supported. That would make the problem (much) worse.