Constant Multiplication behavior in FPGAs Ready before Synthesis/Compilation?

[thej178]

Curious and couldn't find this information when browsing:

In my LabVIEW FPGA VI, I have a multiplication of two constants that are used elsewhere. (Why you ask? Those two values are used in other other operations separately, so it made sense to simply multiply them in this block of code instead of hardcoding their multiplied value). My question is, is LabVIEW optimization smart enough to precompute this value before synthesis since they are readily available or not?

(Any other information in regards of syntehsis itself is welcomed).

[GerdW]

Hi j,

the LabVIEW compiler is pretty good at "constant folding" - atleast on Windows targets.

I guess this also applies for other targets the same way…

(Read the LabVIEW help on this feature.)

[Intaris]

Yes, as long as you don't use Xilinx IP to do it.....

A standard LV multiplier should not prevent these being constant folded.

[thej178]

Thank you @GerdW and @Intaris! I didn't know that this is even called constant folding. I appreciate the insight!

[cbutcher]

Some detailed description of the LabVIEW compiler can be found here: NI LabVIEW Compiler: Under the Hood

A section copied from that document reads:

For example, an implementation of a constant folding optimization that runs on a DFIR graph can be written once and applied to desktop, real-time, FPGA, and embedded targets.

It describes the way in which by using various levels of representation, some optimizations can be run before a specific target is 'targeted'.