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Can I export VHDL from Labview FPGA?


We have a situation where existing Labview FPGA code works, but we need to embed it into an environment where we can't run Labview.  So we're considering taking the VHDL generated by Labview FPGA and porting it to another FPGA.

To do that, we need to get our hands on the VHDL output.  How does one do that?


Peter H.

PS: If could find an FPGA forum, I would post my question there...
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Message 1 of 11
Hi Peter,
There is no way to get to the VHDL generated by Labview FPGA. 
Message 2 of 11

Hi Peter

I do not think there is a easy way to see the VHDL code.

Althought the FPGA toolkit is using the VHDL as an intermediate step before binary code.

take care



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Message 3 of 11
As Brian and Pawel indicated, there is currently no way to access the LabVIEW generated VHDL code.
Matt S.
Applications Engineering
National Instruments
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Message 4 of 11


I have the same question als PGH: Is it possible to export/generate VHDL-Code from LabView? But your answers are about 7 Years old, so i would like to ask if something changed in this time.

And i have another question:

If its still not possible to export VHDL-Code directly out of LabView, Labview can generate C-Code by a C-Code-Generator. Is it possible to generate C-Code out of LabView-FPGA-Projects and to transform this C-Code with translators to VHDL-Code ? I have found some news that say there exists such translators. Did National Instruments sell solutions like that oder solutions that can generate VHDL-Code in other ways?

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Message 5 of 11

Hi M.,


yes, there is a translator to C. Just call your local NI representative. Take a seat before asking for the price 😄

Best regards,

using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 6 of 11

So there is still no way to generate VHDL-Code directly out of LabView ? For example to use it to develop an equalent ASIC ?

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Message 7 of 11

Are you in any way related to Incanus?


The very same question of a new member of the forum?

Best regards,

using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 8 of 11


I have the same problem: I want to genrate the vhdl code from labview. Did you find a solution??

Thanks in advance.

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Message 9 of 11

I believe in newer versions of LV FPGA, this is supported. I don't know which version was the first to support it though.


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Message 10 of 11