Hello, We have a situation where existing Labview FPGA code works, but we need to embed it into an environment where we can't run Labview. So we're considering taking the VHDL generated by Labview FPGA and porting it to another FPGA. To do that, we need to get our hands on the VHDL output. How does one do that? Thanks, Peter H. PS: If could find an FPGA forum, I would post my question there...

LabVIEW

This exports to a Vivado project but the VHDL from LabVIEW FPGA is locked. From the above link:

"All the design files generated for the export are encrypted except those with filenames that start with UserRTL_."

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