Are shift registers on RT deterministic or not?

[Lee_Jay]

I've done some searching and have found conflicting answers to this question.  In some places I've found that shift registers call the OS memory manager and therefore make time-critical VIs non-deterministic.  In other places, I've found recommendations to use shift registers on an RT for the purpose of making the system detministic.

So which is it?  Does anyone have a definitive answer?

Lee Jay

[Ben]

Hi Lee Jay,

You wrote "In some places I've found that shift registers call the OS memory manager and therefore make time-critical VIs non-deterministic."

Could you please point me to where you found that?

The presense of a SR in code does not make the code deterministic or non. They are simply buffers.

There are both deterministic and non-deterministic operations that can be performed on these buffers.

An example of an operation that CAN be non-determinisitic is "build Array" which will increase the amount of memory required to store the data. If the amount of memory allocated for the buffer is not sufficient to store the data, then the memory manager will be called to increase the buffer size before the updated array is stored away. The call to the memory manager is what is non-deterministic.

An example of an operation that is determinisitic is "Replace array subset". Since the the size of the array does not change, there is no need to allocate more memory so the memory manager is never called.

If you want to determine in the memory manager will be involved in an operation, then you should determine where buffers are being allocated. This can be done using

Tools >>> Advanced >>> Show Buffer Allocation

(In LV 7.1, I have no idea where they hid that for LV8)

I hope that helps,

Ben

[Lee_Jay]

I think I may have misread the message that led me to think that.  Now that I read it again, it doesn't say what I thought it said.  However, that message is below:

http://forums.ni.com/ni/board/message?board.id=280&message.id=1690&query.id=58696#M1690

I'm still a bit confused as to whether or not a shift register calls the memory manager to allocate the buffer in the first place and whether or not that operation can be relied upon to execute in a consistent period of time on an RT target.  I have a complex RT code that is executing very inconsistently (varying by a factor of approximately 20) and so I am trying to track down best practices for deterministic RT programming.  I'm getting help with that through NI next week but I'm trying to educate myself in advance.

Thanks for your help.

Lee Jay

[Ben]

I have been developing Rt apps in LV for years.

SR's are a critical part of my TC loops.

There too many issues htat affect determinism to list here and now.

Post your code and we can take a look and may be able to advise. If I have time I'll try to follow-up.

Please post in the earliest version of LV you can. That will maximize the number of people that can help you!

Ben

[Lee_Jay]

You've answered the question I really asked so, for now, I think I'll go away until I talk to NI and fell like I have my arms around the actual problem.

Thank you again.

Lee Jay

[tst]

And here is a method for making sure that you allocate the memory just once.