4-wire protocol of Trigger IDL does not work against back pressure, when it is with 8 or more SPCs.

[UMASO]

Hello, Edge.vi in "niIInstr Data Trigger v1 FPGA.lvlib" has interface of 4-wire protocol.  However, its 4-wire does not seem work properly, when it handles 8 or more 8 SPCs.  When it handles 8 or more samples, "data in" and "input valid" are pipelined, but the registers are not controlled but just pipelined.  Please check out inside of the case structure below.  

"Get Trigger Index.vi" has also the same problem, as its pipelining registers are not controlled for 4-wire protocol.  

Would NI recognize this situation?  If so, would they plan to fix this?

IDLs are fantastic products for all LabVIEW FPGA users, as it has opened up core of instrumentations such as VSTs, 517x/5164, FlexRIOs, etc.  

I hope NI keeps maitaning and adding these componenets.  Thanks for the invention of IDL and LabVIEW FPGA.