LV2010 Merge Errors Improvement

[JB]

Unlike the other growable functions (eg Build Array, Concatenate Strings), the output of the really appreciated new Merge Errors function shouldn't be centered to avoid a bend in the error wire.

[tst]

If you don't want a bend in the wire, then place the node in such a way that there will not be a bend in the wire.

All growable nodes have the single I/O in the center and I don't see why this should be different.

[crossrulz]

I would actually love to see this and the build array have the output terminal on the top.  It always annoys me having that bend in the wire with my while loops w\ shift register.

[tst]

I agree about the SR bend annoyance. The same happens when you build an array inside a case structure.

I might agree to a more generic idea, which would be to add a right click option to some (all?) of the growable nodes to allow their single input/output to be at the top, center or bottom. This will also help eliminate the bends you get when you enlarge bundle/unbundle nodes. I still don't like the non-standard behavior, but it certainly has merit.

[elset191]

Why not just put the bend behind the node?

[jlokanis]

elset191: because that would be bad style.  And VI Analyzer would ding you on that.

[JB]

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tst a écrit :

If you don't want a bend in the wire, then place the node in such a way that there will not be a bend in the wire.

All growable nodes have the single I/O in the center and I don't see why this should be different.

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In most of my code, I align the VIs on the error wire. The alignement would be easier if the output was on the top --> aligned with the first input. Cleaner code, less time to align the VIs...

[JB]

If you don't want a bend in the wire, then place the node in such a way that there will not be a bend in the wire.

All growable nodes have the single I/O in the center and I don't see why this should be different.

[elset191]

elset191: because that would be bad style.  And VI Analyzer would ding you on that.

Meh.  Such a minor infraction doesn't bother me.  When the style guidelines make my block diagram look worse, I tend to not follow them.  Especially for something like this case.  And I don't have the VI Analyzer to yell at me, so...double win.

[Darren]

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@jlokanis wrote:

because that would be bad style.  And VI Analyzer would ding you on that.

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The only two VI Analyzer tests I can think of where this would apply are the Wire Bends test and the Backwards Wires test, both of which have an option (which is selected by default) to ignore wire segments that are under their own source/sink terminals.

[Darren]

Available in LabVIEW NXG. The output of the Merge Error (or Retain First Error) node is always on the top right corner of the node.

[JB]

Many thanks.