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Terry_ALE

Simulation Mode for CLIP

Status: New

Can support for simulating CLIP nodes (as can be done with IP Integration Node) be provided in LabVIEW FPGA?

 


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
2 Comments
nanocyte
Active Participant

I think this is the default. I dropped an IP integration node on my block diagram and I was able to run it in simulation. I believe during the setup of the node, the xilinx synthesizer generates a DLL in the background.

Terry_ALE
Active Participant

Indeed IP Integration Node does simulate.

 

CLIP does not.  The containing VI will 'run' in simulation mode but the outputs are not expected to be meaningful.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications