LabVIEW FPGA Idea Exchange
In labview it is not allowed to exit SCTL running in an external clock domain. Labview claims it could lead to instability of code due to glitches etc on the external clock.
I propose to leave the option open to the programmer to take that risk, which is not always there. It can lead to better understandable code.
For example I have code where I read data from an NI5752 ADC module and store in in block RAM (32 ADc channels, 32 block RAMs). Reading from that ADC implies acquiring the data in the external ADC clock domain. So, also the writing to memory is in that clock domain.
I needed to implement a function to reset the memory as well. That means writing to that memory. That has to be done in an SCTL in the same external clock domain.
However, this reset function (subVI) can no be inserted in the normal "enable chain" of the main program, since the SCTL can not be terminated and the memory reset subVI never terminates.
Now I had to make an ugly trick to get this done. In the main program I create a dead branch doing the reset. That subVI never stops, but after the reset has been done it send a signal via a FIFO to the "wait reset" subVI in the main enable chain. the wait reset is running in the default clock domain and can exit the wait loop after the reset signal has been received.
However, this trick is not easy to understand from the program. It would have been easier if the reset function (external clocked loop) could have exited by itself and be inserted in the main enable chain. That would have been more logical..
