LabVIEW FPGA Idea Exchange

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gsussman

Allows locking of parts of the block diagram to minimize compile time

Status: New

When working with LabVIEW FPGA if so much as the value of a block diagram constant is changed, the entire application must be recompiled.

 

It seems that there could be a smarter method to deal with recompiling that might allow selected portions of the block diagram to be recompiled without the need to recompile the entire app.

Some of the tradeoffs might be lower FPGA utilization efficency and timing constraints, but allowing minor changes to the FPGA code without the overhead of a complete recompile would certainly make debugging applications much faster.

 

I am not necessarily proposing an implementation just posting an idea that seems like it would add value to the LV-FPGA development experience.