Using the LabVIEW 2012 FPGA Control on CompactRIO Sample Project

[Darren]

The Change State button is set to Latch mechanical action:

This means that once the value of the Change State terminal is read on the diagram of FPGA Main.vi, it will latch back to its default state of FALSE.

[ctVolFan]

There doesn't seem to be a way to stop the RT Main.vi running on the cRIO. The document on "...Overveiw of Architeture..." by Meghan August 2012 states on page 29 that pressing the "Exit on the UI Main.vi will cause the RT Main "Exit" case to execute, but this doesn't happen. The code is not setup to do this.

What do you think should be done to bring the RT Main.vi to an orderly Exit?

[MeghanK]

When the user hits "Exit" on the UI, this case below executes on RT, which should in fact stop all of the RT loops, put the FPGA into a safe state, and then shut down the FPGA VI by closing the reference, and then lastly, restarts the RT system. When you send the "Exit" command, are you receiving any error messages displayed to the UI that may indicate that the message was not received? Does the UI exit, and the RT Main continues to run?

[ctVolFan]

The UI Main does not send an Exit message to the RT Main. I'm wondering if you have a different version of the project than what is supplied with LabView.

[Darren]

These sample projects were designed to have UIs that can disconnect and reconnect to a continuously running RT Main VI on the cRIO. Consistent with this design, clicking the Exit button in the UI will *not* stop the RT Main VI. This allows you to re-run the UI Main VI and re-connect to an RT Main VI that is already running on a cRIO system.

If you want the UI Main VI to stop the RT Main VI on exit, then you can add the code in the blue sequence structure to the "Exit" message of the UI Main VI:

[ctVolFan]

Darren - Thanks! First: this makes sense and will be what we need for the final system. Second: I'm not going crazy after all, which is a little bit of a relief.

I would strongly suggest updating the documentation on this sample project. This is one item to change for sure. Also; 1) The FPGA Reference is a typedef and has to be updated if controls or indicators are added to the FPGA Main. (BTW - why is this a typedef?)

And, 2) The Close FPGA VI Reference needs to be changed to "Close" instead of "Close & Reset" if the project is to work as described with the fpga bitfile in flash and always running to keep safe-state outputs in place.

These things may seem trivial but they will stop someone in their tracks for quite a while. especially someone who is still learning to work with the cRIO.

Thanks again!