TNT4882

[Shamsan]

TNT4882 in Turbo-7210 mode

=====================

// chip reset

// WriteTNTreg(AUXMR,0x02);    

//1-Soft Reset
 WriteTNTreg(CMDR,0x22);  //1
 

//2-Place the TNT4882 in Turbo+7210 Mode

WriteTNTreg(HSSEL,0x00); //2

WriteTNTreg(SPMR,0x80);  //3

 WriteTNTreg(AUXMR,0x80); //4

 WriteTNTreg(SPMR,0x99);  //5

 WriteTNTreg(AUXMR,0x99); //6

 
 WriteTNTreg(AUXMR,0x02); //7
  WriteTNTreg(AUXMR,0x8E); /*<AUXRA> *///8
  WriteTNTreg(AUXMR,0xA8); /*<AUXRB> *///9
  WriteTNTreg(AUXMR,0x49); /*<AUXRG> *//11
  WriteTNTreg(AUXMR,0xE4); /*<AUXRI> //SISB=0, reading ISRx clears it*///12

WriteTNTreg(AUXMR,0x50);  //Page in IMR0
 WriteTNTreg(0x0C,0x80);   // IMR0

 WriteTNTreg(IMR1,0x10);   //INT on ENDRX is ENABLED
 WriteTNTreg(IMR2,0x00);   // not used

 WriteTNTreg(AUXMR,0x50);  //Page in ISR0
 ReadTNTreg(0x0C,&general);  // clear ISR0

 ReadTNTreg(ISR1,&general); // clear ISR1
 ReadTNTreg(ISR2,&general); // clear ISR2

  WriteTNTreg(AUXMR,0xE5); /*<AUXRI> //SISB=1, reading ISRx doesn'tclears it*/

 WriteTNTreg(ADMR,0x31);
 WriteTNTreg(ADR,GPIBaddress);
 WriteTNTreg(ADR,0xE0);

 WriteTNTreg(SPMR,0x00);
 WriteTNTreg(CMDR,0x04); //go clear stop and halt

 WriteTNTreg(EOSR,0x0A);   //EOSR=line feed
 WriteTNTreg(AUXMR,0x8E);  // AUXRA: Enable EOS

 WriteTNTreg(IMR3,0x02);  //Enable END RX

 WriteTNTreg(AUXMR,0x00); //6 clear PO msg
 WriteTNTreg(AUXMR,0x03); //Finish Handshake(rhdf)

I used the chip in One-Chip mode and it worked. I set the above initialization to switch the chip to Turbo+7210 mode

I couldn't get it to generate interrupt. Is there anything missing in the above initialization?

Thanks

[Collin M]

Why are you using Turbo+7210 mode? The only reason for this mode is to emulate older designs that had a separate ASICs and the same board. One-chip mode should be used for new designs.

[Shamsan]

Thanks Mr. Collin,

In my previous design, I used NAT7210 chip and worked fine for me . Therefore, I want to implement NAT7210 in TNT4882.

I tried to use One-chip mode, using interrupts, but sometimes I read from the buffer (FIFOB) what I wrote which makes the system hangs.

I meant randomly, sometimes the data in FIFOB gets mixed up from the point view of TX and RX.

Rather than spending much time on One-chip mode, I'll implement NAT7210 and later on in the future I would try again to implement

one-ship mode.

Now I cloudn't get it generates an interrupt, there is no handshaking between GPIB-PCI and my chip. I'm thinking there is something

missing which suppose to make the chip active. Do you have any idea?

[Collin M]

I need to make some additional comments before commenting on your firmware. There is no "NAT7210" mode in the TNT4882. There is a "Turbo+7210" mode that emulates two chips; the NAT7210 and Turbo. The Turbo ASIC contains the transfer manager and FIFOs among other things. These were not part of the original NAT7210. One-chip mode has all the same registers and a very similar interface to "Turbo+7210" mode but has a cleaner interface. The code you need to add to support the Turbo is essentially the same as the code for supporting One-chip mode. With One-chip mode you don't have to worrry about things like paging in registers. Also, "Turbo+7210" mode is not supported in the latest GPIB ASIC (TNT5002) and will not be supported in future ASICs. You should seriously consider using One-chip mode instead of Turbo+7210 mode. I am not aware of any other customer who has ever used Turbo+7210 mode, they all use One-chip mode.


When you write 0x02 to the AUXMR at step //7 you are clearing most of the configuration you have already done.

If the mode pin is pulled up or floating the TNT4882 will be in Turbo+7210 mode by default. No other configuration is needed to enter Turbo+7210 mode.

When you write the GO command is that part of initialization or are you actively doing a transfer? It appears you write GO prior to clearing the pon message. Typically the GO command is not written until all the setup is done for a particular transfer. GO should not be written until the TNT4882 is about ready to perform a transfer.

My recommendation is that you separate your code into an initialization section and data transfer section.

[Shamsan]

TNT4882 in Turbo-7210 mode

=====================

// chip reset

// WriteTNTreg(AUXMR,0x02);    

//1-Soft Reset
 WriteTNTreg(CMDR,0x22);  //1
 

//2-Place the TNT4882 in Turbo+7210 Mode

WriteTNTreg(HSSEL,0x00); //2

WriteTNTreg(SPMR,0x80);  //3

 WriteTNTreg(AUXMR,0x80); //4

 WriteTNTreg(SPMR,0x99);  //5

 WriteTNTreg(AUXMR,0x99); //6

  WriteTNTreg(AUXMR,0x8E); /*<AUXRA> *///8
  WriteTNTreg(AUXMR,0xA8); /*<AUXRB> *///9
  WriteTNTreg(AUXMR,0x49); /*<AUXRG> *//11
  WriteTNTreg(AUXMR,0xE4); /*<AUXRI> //SISB=0, reading ISRx clears it*///12

WriteTNTreg(AUXMR,0x50);  //Page in IMR0
 WriteTNTreg(0x0C,0x80);   // IMR0

 WriteTNTreg(IMR1,0x10);   //INT on ENDRX is ENABLED
 WriteTNTreg(IMR2,0x00);   // not used

 WriteTNTreg(IMR3,0x02);  //Enable END RX INT

 WriteTNTreg(AUXMR,0x50);  //Page in ISR0
 ReadTNTreg(0x0C,&general);  // clear ISR0

 ReadTNTreg(ISR1,&general); // clear ISR1
 ReadTNTreg(ISR2,&general); // clear ISR2

  WriteTNTreg(AUXMR,0xE5); /*<AUXRI> //SISB=1, reading ISRx doesn'tclears it*/

 WriteTNTreg(ADMR,0x31);
 WriteTNTreg(ADR,GPIBaddress);
 WriteTNTreg(ADR,0xE0);

 WriteTNTreg(SPMR,0x00);

 WriteTNTreg(EOSR,0x0A);   //EOSR=line feed
 WriteTNTreg(AUXMR,0x8E);  // AUXRA: Enable EOS

 WriteTNTreg(AUXMR,0x00); //6 clear PO msg
 WriteTNTreg(AUXMR,0x03); //Finish Handshake(rhdf)

 WriteTNTreg(CMDR,0x04); //go clear stop and halt

Thank Mr. Collin,

All the above is initialization sequence. Regardless of it, no interrupt is generated by the chip when GPIB-PCI tried to talk to the chip.

[Collin M]

What interrupt are you expecting?

Are you saying you perform the sequence above every time the device is powered on?

[Shamsan]

Yes I perform them.

I'm expecting TLCINT interrupt.

[Collin M]

TLCINT is just the logical OR of the interrupts in ISR0, 1, and 2. Which interrupt in ISR0, 1 or 2 are you expecting to assert?

[Shamsan]

I'm expecting END RX which is  ISR1 bit 4

[Collin M]

The END RX interrupt sets at the end of receiving a GPIB data transfer. In order to receive a GPIB data transfer there is some required configuration. At a minimum you must set the IN bit in the CFG register to '1' to configure the FIFO for receiving data, and write the byte count to the COUNT . Remember, you now are functionally programming a Turbo488 in addition to a 7210. Figure 2-1 in the TNT4882 programming manual shows a diagram of this. You are also the first customer I know of in 10 years who has attempted this.

You should not write the GO command until you expect a data transfer to start. A data transfer cannot start until the TNT4882 is addressed as a talker or listener. I don't see that you ever check if you are a listener.

I think it would be very helpful for you to read chapter 4 of the TNT4882 programming manual. This explains in detail the necessary initialization and configuration.