NAT7210 Programing

[vibro]

Hello!
I have a question.

I want to use NAT7210 (in 7210-Mode) as a controller.

The offset of IMR0 and the offset of ADR are the same.

Isn't there problem even if I write the mask setting of ISR0 to IMR0 after writing
the primary address setting to ADR?

Are these two writing distinguished?
Are there any procedures?

[Steven_T]

Vibro,

You are correct.  There is a way to write to both registers.  If you notice, IMR0 has a bold box around it.  This means that it is a paged register.  You write to this register only if you place a page in command before setting the value of the register.  You can set the page-in state to true by writing the page-in auxiliary command to the auxiliary mode register.

This information is detailed in page 3-2 and 3-3 of the manual: http://www.ni.com/pdf/manuals/370875a.pdf

I hope this helps!

Steven Trahan
National Instruments

[vibro]

Hello Steven-san

Thank you for your E-mail.

I did not understand the usage of page-in(AUXMR).
Please teach me.

For instance, what procedure is it when ADR and IMR0 are set?

ex.  primary GPIB address = 30(1E h)

1.      write 0x1E in offset 6 (ADR).
2.  ?   write 0x50 in offset A (AUXMR).
3.  ?   write 0x00 in offset 6 (IMR0).

As for READ and WRITE, I do not understand order.

[Steven_T]

Hello Vibro,

You are correct.  Any time you need to access one of the paged registers, you need to get into the Page In state.  This state only lasts through the first memory read or write, so you need to get back into the Page In state in order to access more than one paged register.

So the way to set the primary address of 30 is exactly the way wrote. 

I'm not completely sure what you mean by the order of read and write.  Please clarify and I will be happy to help further.

Steven Trahan
National Instruments

[vibro]

Hello Steven-san

Thank you for the E-mail.

The writing of my question was insufficient.
Please let me reconfirm it.

The following are written in the manual 3-3 page.
---
How to Page-In
The NAT7210 enters the Page-In state when the host interface writes the Page-In
auxiliary command to the Auxiliary Mode Register (AUXMR). The NAT7210 registers
appear at their Page-In state offset for the first register access after the Page-In command.
The NAT7210 leaves the Page-In state at the end of the first register access after the
Page-In command.
---

I do not completely understand this explanation.

I want to write 0x1E(Address=30) in ADR, and I want to write 0x00 in IMR0.
***************************************************
START
            Page-In state is False.

STEP1.      write 0x1E in offset 6 (ADR).

STEP2.      write 0x50 in offset A (AUXMR).
            Page-In state is True.

STEP3.      write 0x00 in offset 6 (IMR0).

Next...

STEP4.      write 0x50 in offset A (AUXMR).
            Page-In state is False.

Next...

STEP5       write 0x00 in offset 6 (IMR0? or ADR?).

END
***************************************************

For the above-mentioned,
> Is ADR unshaded register at STEP1 ?
> Is IMR0 shaded register at STEP3 ?

In addition...
> Is register previously accessed unshaded register, and is register accessed later unshaded register?

> Why is it decided to ADR at STEP1 ?

このメッセージは　02-15-2007 10:53 PMに vibro が編集しています。

[Steven_T]

Hello Vibro,

I think I understand where the problem is.  The manual states when the page in state is set to false.  It is immediately after the first register access.

--

The NAT7210 leaves the Page-In state at the end of the first register access after the
Page-In command.
--

Now lets look at your code 🙂

I want to write 0x1E(Address=30) in ADR, and I want to write 0x00 in IMR0.
***************************************************
START
            Page-In state is False.

STEP1.      write 0x1E in offset 6 (ADR).

STEP2.      write 0x50 in offset A (AUXMR).
            Page-In state is True.

STEP3.      write 0x00 in offset 6 (IMR0).

            Page-In state is False after the first regiser access. (you just wrote to a paged register)

Next...

STEP4.      write 0x50 in offset A (AUXMR).
            Page-In state is False.  Page-In state is True.

Next...

STEP5       write 0x00 in offset 6 (IMR0? or ADR?).  -Since Page-In state is True 0x00 will write to IMR0.

END
***************************************************

ADR is unshaded, so it is not a paged register.  The Page-In state must be false in order to access it.  IMR0 is shaded, so you must have Page-In state true to write to it.  Shaded just means that a register is a paged register.

Assuming that the Page-In state starts false in this part of your program then ADR will be accessed at step 1.  Otherwise it would access IMR0.

I hope this helps!  Let me know.

Steven T.

[vibro]

Hello Steven-san

Thank you very much for the e-mail.

I understood for Page-In thanks to your kind explanation.

I had overlooked "The part of page 3-2 is enclosed by the bold line is Paged-Register".

I will try some READ/WRITE.