SPI IP

[Ryan_V[DE]]

SPI IP » This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality.

Description: Serial Peripheral Interface (SPI) buses are commonly used to communicate between a controller (master) device and a target (slave) device. In general, SPI buses require four lines for communication: chip select/clock enable, serial clock, master serial data out (MOSI), and master serial data in (MISO). In some cases only a subset of these lines are used; some devices multiplex both MOSI and MISO onto a single bidirectional data line. This IP includes LabVIEW FPGA code for both an SPI master and an SPI slave.

Additional Documentation:

• After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI SPI IP\documentation\NI 5644R Serial Peripheral Interface (SPI) Example.pdf

Compatibility:

• LabVIEW Versions: 2012
• Verified hardware targets: NI PXIe-5644R, NI PXIe-5645R
• Links to relevant examples: SPI Example for the NI PXIe-5644R NI SPI Host Example for the PXIe-5644/45R

Dependencies:

• none

Performance:

• 3 and 4-wire interfaces
• Up to 64 bit word lengths
• Programmable clock frequency

FPGA Footprint:

Xilinx Virtex-6 LX195T

• 0.6% / 783 LUTs
• 0.5% / 1182 Flip-Flops
• 0.0% / 0 Block RAMs
• 0.0% / 0 DSP Slices
• 200 MHz clock rate

Latest Version:

• SPI IP 1.0.0 (LabVIEW 2012)

Previous Versions:

• none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager