Automotive Engine Simulation Library for HIL

[Bhakti_Kalghatgi]

We are using NI AES library for simulating engine on PXI HIL system.

Plant model is built in Matlab which gets converted to *.dll file and then loaded on PXI using Veristand.

Here we are using AES library for

1. Generating RPM signal.
2. Decoding start angle, end angle and duration for injector and ignition signals from ECU. ( Vi used is AES ECU Event Measurement - All Measurements.vi)

The issue observed in this is when injector pulse is made OFF the AES block should give duration as ‘0ms’ however it gets latched to last duration observed.

This is creating problem while simulating malfunctioning of injector.

Test case is : If injector is made off,ON duration is ‘0ms’ and hence RPM will decrease.   Case result is Failed.

Normal test case: Engine running in normal condition, injector duration is observed properly.

Please help us to resolve this issue.

Thank You,

Regards,

Bhakti Kalghatgi

[StephenB]

Hi Bhakti,

Unfortunately they is a known issue. I have experienced this before myself.

The reason is, the event measurement VI does not timeout. So if the pulses stop, it still reports the last pulse values. Until we have a chance to fix this, you can fix it yourself by editing the AES ECU Event Measurement - All Measurements. vi to add a timeout.

For my future reference, what would you prefer the timeout units to be in? Cycles of the engine or time?

[Bhakti_Kalghatgi]

Ok Stephen. Thank you for your prompt reply.

We would like the time out in terms of crank angle rotation. If no injector pulse is found within 720 deg of rotation then it should show the injector pulse width as zero.

As you said we need to edit the vi,but how can we add this angle timeout.

Please guide us on this.

Regards,

Bhakti Kalghatgi.

[StephenB]

Hi Bhakti,

I was suggesting that you make the modifications yourself. Since the code is open source, it shouldn't be too difficult to modify it to meet your needs. I suggested this because you might have the skills and time to do it faster than my schedule lets me get to it.

I would also like to understand your needs better, so this could be incorporated into the AES distribution in the future. So I have some questions:

1. When you say "If no injector pulse is found within 720 deg of rotation", do you mean no pulse for 720 degrees of rotation since the last pulse?
2. You are capturing events referenced to the crank angle (0-360), but you want the events to time out after 720 degrees (a full cycle) of no pulse. Is this correct? If you were capturing events from cycle angle (0-720) would you want it to time out after 720 degrees of no pulse as well or 1440 degrees?
3. The outputs are "Start Angle (degrees)" "End Angle (degrees)" "Angle Duration (degrees)" and "Time Duration (clock ticks)". If the event times out... I can set the durations to 0, but what shoudl the start and end angle be? I was thinking an extra boolean output for "timed out" and leaving start/end angle at their last value.

Thanks!

[Bhakti_Kalghatgi]

Hi Stephen,

Thanks for your reply.

Actually i just need the time duration(ticks) to be zero.

Even if the start and end angle values get latched to their previous values its fine for our application.

Are u planning to execute this change and update the library?

[StephenB]

I will try, but I don't know when I will have time to finish. Maybe today, maybe next month.

Can you answer question #1 and #2 above?

Thanks

[Bhakti_Kalghatgi]

Hi Stephen,

When we say 'If no injector pulse is found within 720 deg of rotation' it means 720 deg of crank rotation(2 revolutions of crank shaft). This can be considered as 1440 deg which corresponds to 4 rotations of crank shaft.

Hope this gives proper explanation.

Thank you

Bhakti

[zpfenghust]

Hi,StephenB,

Excuse me,I have encounter a custom device problem.It's difference with the topic,but i need your help to slove the problem.The phenomenon is that i modified the Labview VI by adding some output,but i cann't read the data on Veristand GUI.The sequence is:

1.change the cam-crank vi  in project

2.compile it.

3.Upload the FPGA btfile in Custom device RT Driver and add the output array in loop.

4.Build configuration and engine 

5.Using veristand call new Custome device(system explore,mapping,deploy and then run workspace)

But the Veristand can only read these data that pre-vi include.I guess the reason is whether or not the a PXI bug.That means the new cam-crank vi complied btfile doesn't deploy into PXI device.

Hope your promptly reply.

Best Regards,

Peter

[BKennedy]

Hey Guys!

We're using the Fully Custom FPGA code and we can only code 32 teeth, but we need 81. Y'all recommended I look in the AES Fully Customizable Teeth Generation.vi and check the vi-local memory, which is only 64 elements big. After expanding the size to 162, it works!

I have a request, would you mind putting this limitation and its fix in the documentation? Or up the memory block size in the next rev. Though that does make a larger bitfile. Your call though!

Thanks!

Bryan

[StephenB]

Good catch Bryan! I'll put that in the docs for now and try to incorporate a better fix for a future revision