Restrictions to LV-functions for modelling?

[frankkremer]

Hello,

I use LabVIEW 2011 to create a model (.lvmodel) for Veristand 2011.

It works if I import a VI with only simple numeric functions.

When I try to import a more complex one the compilation process is aborted.

What LV-functions can I use in a model?

I currently try to use while-loops (with shift-registers), queues, events, case-structures, sequences, tick-count, numeric, bolean and comparison functions.

There are clusters, DBL, I64 and U8 variables.

I will explore the possibility of using the Control Design and Simulation Module for a new design, but it would be very useful to know what went wrong.

Greetings

Frank

[Jarrod_S.]

I don't know off the top of my head of any limitations in your LV VI for creating an lvmodel. If you could post an example VI that does not build successfully, that would help us out.

[frankkremer]

Here is my VI. It is only a prototype, but I don't see why it shouldn't work.

(LV 2011)

[Devin_K]

The VI compiled fine on my system.  Perhaps it's an issue with the localised version of LabVIEW you're using?  I assume you're using a German version?

I have attachched the built version if you want to try it out.  (Just rename it to regler-modell v1.lvmodel.  Apparently the forum doesn't allow ".lvmodel" attachments)

[frankkremer]

Sorry, perhaps I should have explained it better.

The compilation of a .lvmodel-file works just fine.

I can also import the model into VeriStand. But if I want to run the VeriStand-project the compilation always stops at "Starting deployment group 1".

The project is new and there is nothing else but the imported model defined. I have no problem starting other VeriStand projects.

This led me to the conclusion that I used LV-functions that are not allowed for a VeriStand model.

[Jarrod_S. · Accepted solution]

Thanks for the clarification. I think I see what is happening.

Models should be designed to run and complete immediately. There shouldn't be a loop in the VI that repeats over time. VeriStand itself is responsibel for scheduling the model by invoking it repeatedly every timestep of the control loop (or at some decimation of it). The general thought is that models will simply perform a calculation based on the inputs and parameters and then publish output data.

So it seems your model would just consist of the bottom loop code that does the calculations, but without the loop itself, since VeriStand serves as the loop. You can still have a loop in your model to take advantage of uninitialized shift registers to save state data between runs, but the loop should always have a true wired to the Stop terminal.

[frankkremer]

Thanks, that makes sense.

I will try to redesign the VI tomorrow.

[Jiraiya_Sensei]

Yes, It works! Thanks for the detailed information Jarrod 👍