do you need both daughterboards to use LVFPGA with a USRP ?

[apchar_]

I have an X310 that I just installed one CBX-120 daughtercard into. The other side of the USRP (RF B) is empty.

I was able to run the "niUSRP EX Rx Continuous Async Reconfig on the Fly.vi" in the examples directory, where everything is done on the host.

But I cant run the host vi's in the "NI-USRP Simple Streaming" project that uses the LVFPGA module.

After about 10 seconds, I get an error popup:

Error -1074100588 occurred at Timeout while waiting for: LO Locked

niUsrpRio Config v1 Host.lvlib:Wait until Done.vi:950001

Possible reason(s):

Timeout waiting for operation to complete.
Complete call chain:
     niUsrpRio Config v1 Host.lvlib:Wait until Done.vi:950001
     Configure Frequency.vi:4280001
     Configure Signal (Common).vi:2920001
     Configure Signal (Level).vi:6340001
     Configure Rx.vi:2290001
     Open and Configure Device.vi:6580001
     Rx Streaming (Host).vi

I've disabled the 2nd channel (RF1) on the front panel (& made it the default state.)

Is something is trying to setup the LO in the 2nd channel even though it's disabled ? If so, how do I stop it ? It's too late to buy another cbx-120.

Thanks

[vvkakade]

Hi,

Which NI USRP driver version are you on?

Does the problem replicate if you put the daughterboard in RFB and enable channel 1?

Can you make sure that the DB is pressed firmly into the slot?

Thanks.

[apchar_]

I'm using version 15.0. I havent tried swapping sides. The board is in place & screwed down. It all works fine when doing host side processing. It's just when I use LVFPGA that I get this error. I need the throughput and low latency of FPGA side processing.

Art