derived clock problem?

[VDN1]

Why do I get this error when I set the clock to the "derivedclock"? I'm using USRP 2944R 120Mhz, LabVW comms 2.0

[VDN1]

Help pls

[Bob_Schor]

A little patience, please.  You posted your original question less than an hour ago, in the LabVIEW Forum, posing a question about NI's USRP Product line, when there is a whole USRP Software Radio Forum (search under Additional NI Product Boards) associated with this specialized Products where the chance of reaching someone with USRP experience might be higher.  I'm going to move this request for you as you can't seem to wait ...

Bob Schor

[paigec]

Hi VDN1,

Based on the error "I/O not accessed within required clock domain. Required clock domain: 40 MHz Onboard Clock," it sounds like the clock domain you are hoping to set, DerivedClock, is not within the accepted range. 

To better help you and ensure we fully understand what is happening, I have a few clarifying questions. 

1. What is the error code you see with that error? That appears to be missing from the screenshot provided. 

2. What version of USRP are you using?

3. Where are you defining the DerivedClock? Is that currently set to 120 MHz, per your first post? I'd like to understand what your goal with the clocking is and how you're currently implementing that in LabVIEW Comms.  

4. What happens when you change the clock to the OnboardClock? Does this correct the error? 

5. I noticed that you had posted the same image twice. Was there a different second image that added different context than that currently seen? If so, could you please share that as well? I want to make sure I have all the context on the behavior.

I look forward to the additional context and hope you have a nice day. 

Cheers, 

Paige

[VDN1]

I'm sorry I am not fluent on forums and Im new in this. Thank you for moving my post.

---

@Bob_Schor wrote:

A little patience, please.  You posted your original question less than an hour ago, in the LabVIEW Forum, posing a question about NI's USRP Product line, when there is a whole USRP Software Radio Forum (search under Additional NI Product Boards) associated with this specialized Products where the chance of reaching someone with USRP experience might be higher.  I'm going to move this request for you as you can't seem to wait ...

Bob Schor

---

[VDN1]

First of all thanks so much for replying on my question. The error I mentioned appears when I try to build bitfile to FPGA. By the way, I am using the sample project of labVIEW titled "USRP RIO 120-160 MHz BW Single-Device Streaming". The attached image "img1.PNG" is the Streaming Xcvr (FPGA).gv.. About your questions, 

"1. What is the error code you see with that error? That appears to be missing from the screenshot provided. "

-- There's no error code, or I might be missing it (I'm sorry Im new in Labview). it only says "error" as what is shown on the attached image.

"2. What version of USRP are you using?"

- I'm using 120Mhz usrp 2940 rio

"3. Where are you defining the DerivedClock? Is that currently set to 120 MHz, per your first post? I'd like to understand what your goal with the clocking is and how you're currently implementing that in LabVIEW Comms."

-- I'm not sure what you mean on where do I define the derived clock but I attached an image named "img2.PNG", showing the derived clock I created. I need to increase the clock speed cause I need a faster clock period

"4. What happens when you change the clock to the OnboardClock? Does this correct the error?"

-- It does proceed without error. My question though is why am I unable to setup both the Clock drive loops to have the "derived clock" as inputs? I'm confused. I tried searching on how to properly use derived clocks and streaming xcvr but can't find a clear instruction on how to.

"5. I noticed that you had posted the same image twice. Was there a different second image that added different context than that currently seen? If so, could you please share that as well? I want to make sure I have all the context on the behavior."

-- I mistakenly uploaded it twice. Sorry.

Again thank you for replying. 

[VDN1]

First of all thanks so much for replying on my question. The error I mentioned appears when I try to build bitfile to FPGA. By the way, I am using the sample project of labVIEW titled "USRP RIO 120-160 MHz BW Single-Device Streaming". The attached image "img1.PNG" is the Streaming Xcvr (FPGA).gv.. About your questions, 

"1. What is the error code you see with that error? That appears to be missing from the screenshot provided. "

-- There's no error code, or I might be missing it (I'm sorry Im new in Labview). it only says "error" as what is shown on the attached image.

"2. What version of USRP are you using?"

- I'm using 120Mhz usrp 2940 rio

"3. Where are you defining the DerivedClock? Is that currently set to 120 MHz, per your first post? I'd like to understand what your goal with the clocking is and how you're currently implementing that in LabVIEW Comms."

-- I'm not sure what you mean on where do I define the derived clock but I attached an image named "img2.PNG", showing the derived clock I created. I need to increase the clock speed cause I need a faster clock period

"4. What happens when you change the clock to the OnboardClock? Does this correct the error?"

-- It does proceed without error. My question though is why am I unable to setup both the Clock drive loops to have the "derived clock" as inputs? I'm confused. I tried searching on how to properly use derived clocks and streaming xcvr but can't find a clear instruction on how to.

"5. I noticed that you had posted the same image twice. Was there a different second image that added different context than that currently seen? If so, could you please share that as well? I want to make sure I have all the context on the behavior."

-- I mistakenly uploaded it twice. Sorry.

Again thank you so much for replying. 

[paigec]

Hi VDN1, 

Not a problem! Thanks for sharing that additional information. In terms of the version, I was looking to understand what version of the USRP driver you have installed on your system. You can check that by referring to the Software list on the left-hand side of the NI MAX program, also known as Measurement and Automation Explorer. 

Otherwise, it looks like from your images that the DerivedClock is 120 MHz but the required clock noted in the error is 40 MHz, which we resolved by switching this back to the OnboardClock of 40 MHz. With that, it sounds like the deeper question is related to how we can derive clocks with this device and use the clocking effectively. To address this piece, I think the most helpful guidance to clarify the difference between the two major clock in USRP RIO can be found in the following KnowledgeBase article: What Source Signals Are Used to Derive the FPGA and ADC Clock in USRP RIO? This may better clarify what is and is not flexible for the application. 

Please let us know if that proves helpful and have a great day!

Cheers,

paigec