I have a scheme for USRP where Tx and Rx are processing the same iteration since the time is the essential point for this. most of the bits are synchronized, but the periodic error bits are shown up and said the packet had timestamp that was late or too early. I wonder how to solve this.
after initiating the device there are some process that is done at the Tx and Rx. I think the process at the Tx is taking more time at the Rx. I think that is why it shows some error.
Is there any parameter value that can I change to solve this? or should I change something in the whole diagram?
