NI LabVIEW FPGA Floating-Point Library

[ks30]

Introduction

Note: This library is not officially supported nor this page currently monitored.

Floating point math operations on FPGAs are important for many control and simulation applications. In LabVIEW FPGA, most math operation nodes in the Numeric and Comparison palette support the single-precision floating point data type. However, these primitive nodes cannot run inside a Single-Cycle Timed Loop to achieve higher performance. Additionally, these nodes cannot be configured for resource optimization at the cost of performance. The NI LabVIEW FPGA Floating-Point Library solves this problem by providing IP which can be optimized in the following ways:

1. Resource Optimization: You can save resources by sharing multiple instances of an IP when running outside Single-Cycle Timed Loop. Please note that there is IP in the library that does not support resource sharing. The reason for this is that they use very few resources and resource sharing is not applicable.
2. Performance Optimization: You can achieve better timing performance by running the IP in a Single-Cycle Timed Loop. Please note that only a subset of the IP in the library supports running in this mode.

System Requirements

Software Requirements

The NI LabVIEW FPGA Floating-Point Library was designed and tested with the following software packages:

• LabVIEW 2015 or later
• LabVIEW FPGA 2015 or later

Hardware Requirements

The NI LabVIEW FPGA Floating-Point Library supports compiling and running on all Vivado compatible targets. Please refer to the  Compatibility between Xilinx Compilation Tools and NI FPGA Hardware document to determine if your target utilizes Vivado.

 IP List

The NI Floating-Point Library contains following IP. All IP only supports single-precision floating-point input and output.

IP Names	Supported Outside of Single-Cycle Timed Loop	Supported Inside Single-Cycle Timed Loop
Add Subtract Multiply Divide Increment Decrement Square Square Root Reciprocal Exponential Natural Logarithm Equal Not Equal Greater Greater Or Equal Less Less Or Equal	Yes (with resource sharing)	Yes
Absolute Value Sign Negate Equal To 0 Not Equal To 0 U32 To SGL Cast SGL To U32 Cast	Yes (without resource sharing)	Yes
Scale by Power Of 2 Power Of X Sine Cosine Sine & Cosine Quantizer In Range and Coerce	Yes (with resource sharing)	No

Performance Benchmarks

Inside a Single-Cycle Timed Loop

All IPs used inside a Single-Cycle Timed Loop can be compiled and run at clock rate of 40MHz. The following table shows the latency of all IPs running inside Single-Cycle Timed Loop:

IP Names	Latency in Cycle(s)
Add Subtract Multiply Increment Decrement Square Equal Not Equal Greater Greater Or Equal Less Less Or Equal Absolute Value Sign Negate Equal To 0 Not Equal To 0 U32 To SGL Cast SGL To U32 Cast	0
Divide Square Root Reciprocal	5
Exponential Natural Logarithm	2

Outside a Single-Cycle Timed Loop

All IPs used outside Single-Cycle Timed Loop can be compiled and run at clock rate of 40MHz. The following table shows the ideal latency of all IPs running outside of a Single-Cycle Timed Loop. Please note that this latency could increase when using the resource sharing feature of the library:

IP Names	Ideal Latency in Cycle(s)
Add Subtract Multiply Increment Decrement Square Equal Not Equal Greater Greater Or Equal Less Less Or Equal Absolute Value Sign Negate Equal To 0 Not Equal To 0 U32 To SGL Cast SGL To U32 Cast	1
Divide Square Root Reciprocal	15
Exponential Natural Logarithm	3
Scale by Power Of 2	1
Power Of X	10
Sine Cosine Sine & Cosine	39
Quantizer	32
In Range and Coerce	3

[Pie566942.0]

Unfortunately this library is password protected, so we cannot review it, so we cannot use it in AS9100 design and production test.  Please make the password available, even under NDA, so we can take advantage of this IP.

Regards,

Steve K

[AmitShachaf]

Hi KS30,

I would like to use the library. How do I get the password to make it work for me?