is a DMA FIFO a shared resource on a cRIO

[St3ve]

Hi,

I am writing a DAQ and control system on a cRIO. At the moment I have two independant loops reading two separate DMA FIFOs.

One loop (lower priority) reads all of the channels relatively slowly and passes it along for processing and logging.

The second loop (time critical) contains only one channel required for a control algorithm.

Are separate DMA channels actually a single shared resource? Is this going to cause a priority inversion and jitter in the application?

Many thanks for any help,

Steve.

[Christian_Hartshorne_NIUK]

Hi Steve,

Thankyou for your query, I have been looking into this problem for you. For real time applications, shared resources are global variables, non-reentrant sub VIs, LabVIEW memory manager, queues, semaphores and single threaded DLLs etc. More information on shared resources and how they effect determinism in Real Time applications can be found here. An important consideration is weather you are using an RT FIFO, which are by definition deterministic or queues which are not deterministic. For more information on RT FIFOs see this link.

Another important consideration which may dictate whether you experience jitter or a priority inversion is whether the memory manager is called or not. As I have already mentioned the memory manager is a shared resource and it is used to allocate memory in LabVIEW. Since this memory manager is a shared resource, this can cause jitter if we call it within our time critical loops. Avoiding calling the memory manager involves following a number of simple steps like preallocating arrays outside our time critical loop. 

You may also find this link useful which relates specifically to the use of DMA FIFOs for DAQ using the cRIO.

Best Regards,

Christian Hartshorne

Applications Engineer

National Instruments

[Caseyw]

Hi Steve,

To directly address your question, I am fairly confident that each DMA FIFO channel operates independently after initial setup (does not act as a shared resource with other channels). I will verify this with our R&D team to ensure that there aren't any corner-cases that we need to consider, but I think that accessing different DMA FIFO channels from different loops on your real-time VI deterministically should be possible.

Best Regards,

Casey Weltzin

Product Manager, LabVIEW Real-Time

National Instruments

[St3ve]

Hi Casey,

That pretty much answers it!! It will be interesting to find out a bit more about the underlying architecture of the DMA engine.

Many thanks as always!

Steve.