Use DMA FIFOs to send data to and from an FPGA target (bidirectional data transfer)

[HunterSeeker]

Description

Description-Separate-1

Overview

This example demonstrates how to use DMA FIFOs to send data to and from an FPGA target (bidirectional data transfer).

Description

This project is configured to work with a PXI-7841R on a Windows computer, but this same code will work on any FPGA target and a Windows or a Real-Time Host. This example generates a user defined waveform and sends it down to the FPGA using a Host to Target scoped FIFO. The FPGA then sends it right back up to the Host VI using a Target to Host scoped FIFO. In a real application you would want to process data in between, or just use one FIFO for input OR output.

For more general info on using DMA FIFO's check out this link: Creating FIFOs in FPGA VIs (FPGA Module)

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI

 Hardware

• No hardware is necessary to use this example VI. You can migrate this example to any LabVIEW FPGA Target if you want to use real hardware. You must recompile the FPGA VI if you use hardware.
  

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [Host] Main.VI inside the LabVIEW project and follow the instructions on the Front Panel

Additional Information or References

 

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

Description-Separate-2

[HunterSeeker]

Overview

This example demonstrates how to use DMA FIFOs to send data to and from an FPGA target (bidirectional data transfer).

Description

This project is configured to work with a PXI-7841R on a Windows computer, but this same code will work on any FPGA target and a Windows or a Real-Time Host. This example generates a user defined waveform and sends it down to the FPGA using a Host to Target scoped FIFO. The FPGA then sends it right back up to the Host VI using a Target to Host scoped FIFO. In a real application you would want to process data in between, or just use one FIFO for input OR output.

For more general info on using DMA FIFO's check out this link: Creating FIFOs in FPGA VIs (FPGA Module)

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI

 Hardware

• No hardware is necessary to use this example VI. You can migrate this example to any LabVIEW FPGA Target if you want to use real hardware. You must recompile the FPGA VI if you use hardware.
  

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [Host] Main.VI inside the LabVIEW project and follow the instructions on the Front Panel

Additional Information or References

 

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[HunterSeeker]

Overview

This example demonstrates how to use DMA FIFOs to send data to and from an FPGA target (bidirectional data transfer).

Description

This project is configured to work with a PXI-7841R on a Windows computer, but this same code will work on any FPGA target and a Windows or a Real-Time Host. This example generates a user defined waveform and sends it down to the FPGA using a Host to Target scoped FIFO. The FPGA then sends it right back up to the Host VI using a Target to Host scoped FIFO. In a real application you would want to process data in between, or just use one FIFO for input OR output.

For more general info on using DMA FIFO's check out this link: Creating FIFOs in FPGA VIs (FPGA Module)

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI

 Hardware

• No hardware is necessary to use this example VI. You can migrate this example to any LabVIEW FPGA Target if you want to use real hardware. You must recompile the FPGA VI if you use hardware.
  

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [Host] Main.VI inside the LabVIEW project and follow the instructions on the Front Panel

Additional Information or References

 

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[HunterSeeker]

Overview

This example demonstrates how to use DMA FIFOs to send data to and from an FPGA target (bidirectional data transfer).

Description

This project is configured to work with a PXI-7841R on a Windows computer, but this same code will work on any FPGA target and a Windows or a Real-Time Host. This example generates a user defined waveform and sends it down to the FPGA using a Host to Target scoped FIFO. The FPGA then sends it right back up to the Host VI using a Target to Host scoped FIFO. In a real application you would want to process data in between, or just use one FIFO for input OR output.

For more general info on using DMA FIFO's check out this link: Creating FIFOs in FPGA VIs (FPGA Module)

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI

 Hardware

• No hardware is necessary to use this example VI. You can migrate this example to any LabVIEW FPGA Target if you want to use real hardware. You must recompile the FPGA VI if you use hardware.
  

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [Host] Main.VI inside the LabVIEW project and follow the instructions on the Front Panel

Additional Information or References

 

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[HunterSeeker]

Overview

This example demonstrates how to use DMA FIFOs to send data to and from an FPGA target (bidirectional data transfer).

Description

This project is configured to work with a PXI-7841R on a Windows computer, but this same code will work on any FPGA target and a Windows or a Real-Time Host. This example generates a user defined waveform and sends it down to the FPGA using a Host to Target scoped FIFO. The FPGA then sends it right back up to the Host VI using a Target to Host scoped FIFO. In a real application you would want to process data in between, or just use one FIFO for input OR output.

For more general info on using DMA FIFO's check out this link: Creating FIFOs in FPGA VIs (FPGA Module)

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI

 Hardware

• No hardware is necessary to use this example VI. You can migrate this example to any LabVIEW FPGA Target if you want to use real hardware. You must recompile the FPGA VI if you use hardware.
  

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [Host] Main.VI inside the LabVIEW project and follow the instructions on the Front Panel

Additional Information or References

 

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[anonymus]

Worked in simulation, but works incorrectly on FPGA

[HunterSeeker]

How did it behave incorrectly?

[anonymus]

On FPGA you will see the same number collected in sequence. Like 0,0,0 often at start but at other times as well. It is easier to see if you use a know sequence like 1,2,3,...

[davidc10]

Do you have an 8.6.1 version?

[anonymus]

I used 2009 SP1