While Loop Timing _Loop Timer

[Maloya]

I would like this While loop to iterate every second. But it seems it doesen't recognize the Loop Timer. What is wrong?

[crossrulz]

How fast does the loop appear to run?

[Maloya]

Super-fast, when I increase the Count(mSec) it exceeds the maximum simulated time( after one second). Can I configure the simulation speed?

[crossrulz]

Try deploying to real hardware.  Things run a lot faster in simulation mode due to a CPU (2-3GHz) being able to run a lot faster than the fpga clock rate (40MHz).

[crossrulz · Accepted solution]

Just found the Help article talking about this: Debugging FPGA VIs Using Simulation Mode (FPGA Module)

At the bottom, it states:

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Understanding Simulated Time on the Host

If you use certain FPGA resources and you execute the FPGA VI in simulation mode using simulated I/O, the resource uses simulated time instead of real time. Simulated time might be faster than real time depending on the number of events that occur during the simulation. For example, if you add a Wait (Simulated Time) VI to the block diagram and set the delay to 1000 ms, LabVIEW does not attempt to delay one second of real time. Instead, LabVIEW delays as long as necessary before executing the next scheduled action in the simulation.

The following resources use simulated time on the host:

• While Loops
• Single-Cycle Timed Loops
• Wait (Simulated Time) VI
• Loop Timer Express VI
• Tick Count Express VI
• FIFOs, except DMA FIFOs
• Wait on Occurrence with Timeout in Ticks Function
• Interrupt VI, when Wait Until Cleared is TRUE

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