Timed loop on sbRIO accuracy

[roiecoh]

Hello,

I've written a sample program which generates a sinus wave using a timed loop on the linux RTOS and sends the data point to the FPGA using a FIFO buffer.

Each time a data point is sent to the FPGA one of the DIO's changes to indicate a new data point.

I've tested the changes on the DIO using an oscilloscope and getting a huge variability in the timing.

When the sinus generation is implemented on the FPGA the timing as seen by the oscilloscope  is accurate.

I've attached a snippet of the vi which is running on the RTOS and the measurement from the scope. 

Is there a way to get better control of the timing?

Will rewriting the code using C code generate better accuracy?

Thanks

Roie

[MarkCG]

You can write to the FIFO on the real-time side at whatever rate but it's where you read it on the FPGA side that will set the actual rate. Post your FPGA code so we can see that. You also have SIN and COS functions in FPGA so I'm not sure why you need the extra complication of generating the sine wave on the real-time side. 

[nanocyte]

You seem to be writing the point to a FIFO. The FIFOs are not optimized for determinacy but rather for losslessness. You might want to use a top level FPGA control instead. If you do choose to use FIFOs be sure to monitor the timeout/output valid terminal on the FPGA side.

See the TRANSFERRING DATA BETWEEN THE FPGA AND THE HOST SYSTEM section of The NI LabVIEW High-Performance FPGA Developer's Guide for more detail