Accessing CAN 0 port from the sbRio-9627 FPGA - is this possible?

[parsec43]

Can the CAN 0 port be accessed by code running on the FPGA of an sbRio-9627? The diagram on the first page of the manual seems to imply that this is possible, however when adding the 9627's FPGA as a target to a project, the CAN port is not pre-populated as available I/O.

I had a play with the CLIP generator, however this appears to be for adding a second CAN port (CAN 1) that directly utilises FPGA I/O lines through the RMC connector.

This link seems to imply that the CAN port can only be accessed by the RT processor layer, contrary to the manual block diagram.

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P8hdSAC&l=de-DE

Please see the following attachments

1) The block diagram from the sbRio-9627 implying that the CAN 0 port can be interfaced with using the FPGA.

2) An example of the C series implementation of the CAN ports within a project for a CRIO-9073

3) Ideally the expected I/O method that will be available within an FPGA VI.

[nanocyte]

I've never used it but in reading the documentation it sounds similar to the interface for the ethernet port or the other serial ports. It's on the FPGA but dedicated to the RT system so you can't access it through the LabVIEW FPGA interface.

[parsec43]

I suspect you are correct, but it would be nice if the manual was more explicit about this.