Real-Time Measurement and Control

cancel
Showing results for 
Search instead for 
Did you mean: 

PWM

Hi,

 

Can anybody send me the manuals or demos about how to develop PWM. I will use it to generate PWM signals from the ports of Digital output module NI 9476. I am a beginner by the way.

 

Thank You.

0 Kudos
Message 1 of 8
(4,542 Views)

Hello,

 

Since the 9476 is software timed, you are limited to creating this PWM signal in software.  I found this example that can be used for PWM in software with any digital output device.  Here is a newer one that may be simpler to understand.  Here is a good DevZone over PWM in general, but the examples here use counters which will not work since your card is software timed.  Let me know if this works for you, thank you.

Kyle A.
National Instruments
Senior Applications Engineer
0 Kudos
Message 2 of 8
(4,514 Views)

http://zone.ni.com/devzone/cda/tut/p/id/5963

 

Please see the attached link and suggest if it is applicable for NI 9476 (in cRIO) or not for generating the PWM.

 

Thank You.

 

 

0 Kudos
Message 3 of 8
(4,457 Views)

Hey Auree,

 

With a cRIO in FPGA mode, you can do a whole lot more than just what is outlined in that section of your link. That having been said, that seems to be a reasonable calculation for the pulse width desired. Then you need to convert that into the actual signal and output it to the DIO lines. I would recommend looking at the following links for ideas.

This is simply a search for PWM on ni.com/community

http://decibel.ni.com/content/community/search.jspa?peopleEnabled=true&userID=&containerType=&contai...

This example uses normal labview to do PWM, but the concepts should be portable to the FPGA:

http://decibel.ni.com/content/docs/DOC-2066

These are FPGA examples of various PWM-related tasks:

http://decibel.ni.com/content/docs/DOC-2387

http://decibel.ni.com/content/docs/DOC-14124

http://decibel.ni.com/content/docs/DOC-2380

http://decibel.ni.com/content/docs/DOC-13696

 

Obviously most of these will not apply to you, but I just wanted to give you a source of ideas, since the output you need will likely depend on your application.

 

Thanks,

D Smith

0 Kudos
Message 4 of 8
(4,444 Views)

My target is to generate PWM signals through DO port of NI 9476 and read that signal by anlaog input port of NI 9215.

 

I have attached the screenprints.

 

Can you tell me what's wrong with my coding? This is the simplest form of coding for generation of PWM signals.

 

Why I am getting constant DC output from DO port though it is suppossed to generate PWM signal?

 

Your recommendation would be highly appreciated.

 

Thank You.

 

 

0 Kudos
Message 5 of 8
(4,383 Views)

Your host VI is pulling in data from a fxp indicator--that is, it is pulling in a single value at a time--and it is pulling that data every 50 ms due to your wait. You have two options to fix this:
-Replace the fxp indicator with a chart indicator. This is essentially the same as storing a large array on your FPGA, which can waste FPGA space. However, your code (right now) is simple and can probably take the size hit. Then, when you pull data off the chart you are pulling that entire array and placing it on your host VI's chart.
-Replace the fxp indicator and read/write method with a DMA FIFO. Then, on your host VI, begin pulling data out of the fifo.

 

Thanks

0 Kudos
Message 6 of 8
(4,341 Views)

Hi,

 

Could you please look into the attachment and give me suggestions about how to add them?

 

As I marked by encircling with blue ink. I think ther are not controlls or constants. Am I right? If I am, then how to find out them from pallete?

 

And also I need to know (about the lower part graph) what they meant by Currentb period and period count.

 

Your recommendation would be appreciated.

 

Thank You.

 

Regards/

Gopal Sarkar

0 Kudos
Message 7 of 8
(4,295 Views)

Hey, those are old style local variables for those indicators (hence why they have the same names). You can create them just like this:

local.png

 

Those two items seem to simply logic for counting ticks on the FPGA clock until the period resets. It goes high and sets period count to 0, then increments period count until there have been enough ticks with the dio line high, then it switches to low and counts until it has completed the full period, at which point it resets the period count. That is, if you have high 6 and low 4, that logic sets the line high, waits 6 ticks, sets the line low, waits 4 more ticks (until the counter is at 6+4), and then resets the counter.

 

 

0 Kudos
Message 8 of 8
(4,270 Views)