Open FPGA reference - slow?

[tonto_kowalski]

I'm trying to do some data acquisition through a cRIO 9101 attached to DI, DO and AI modules. Right now, I have something like a Read AI VI in my cRIO application that opens the FPGA reference, reads the control (using the read control node), then closes the FPGA reference and returns the read value to the calling VI. My issue is that this seems mindbogglingly slow.

I use this VI and the corresponding DI and DO VIs that are pretty mucht he same internally in a handful of places throughout my code and at least in one spot where I've timed it, it takes something like one full second to run this VI. The culprit seems to be the open FPGA reference VI.

At this point, can anyone suggest what I'm doing wrong?

Is this the right way to go about this, given that my access to the FPGA needs to be fairly scattered throughout my code?

Should I perhaps just write the FPGA reference into a global variable and initialize it once at the start and use it everywhere from the global?

An alternative that I've got going right now is to use the first call VI to only use the open FPGA reference once, then store the reference in a shift register.

Both of these soultiuons create some issues with closing the FPGA reference. Can anyone comment if closing the FPGA reference is really all that necessary?

Thanks,

Chris

[DimensionFinder]

Hi There:

Thank you for contacting National Instruments regarding your support issue. I was wondering how your host VI was structured? I am guessing you are reading the value from your FPGA VI continuously and hence probably have the read control node inside the while loop. It is important to note that the Open FPGA Reference and Close FPGA Reference should not be inside the while loop. If it is, then this is probably whats slowing the program down.

Best Regards,

Jaideep

[tonto_kowalski]

My VI is fairly complex, I do single reads and writes in various locations throughout the code, but never repeatedly in rapid succession. To facilitate this, I had a subVI that just reads analog values from the FPGA and it is within this subVI that I had the sequence of Initialize FPGA ref. --> read --> close FPGA ref. This was the initial solution that was giving me trouble, each call to this sub VI would take a very long time.

My solution right now is to initialize the FPGA reference once at the start of the application and store it in a global, then use that reference every time I do a read/write. This leads to not closing the reference until the application is done, which, in my application, really doesn't happen unless there's a system reboot, power failure, etc. So at the end of my application frequently, the reference will not get closed.

I assume that opening the reference does not store any state information that would survive a reboot (i.e. storing something in flash), so not closing the reference shouldn't be an issue. If anyone has any information to the contrary, please let me know.

Thanks,

Chris

[Doug M]

Chris,
You are definitely on the right track by keeping the reference open.  If you are always accessing the FPGA, then never closing the reference until the application terminates is fine.  Keeping the reference open does a couple of things -- it locks the resources of the FPGA up exclusively for your application, and it communicates periodically with the host VI, so this may include minor persistent network/processor bandwidth, but other than that I cannot think of a reason not to keep the reference open, given the amount of time needed to establish the reference initially.  Losing the reference during a power failure shouldn't be a problem to my knowledge.