AI Cards NI-9202 (x2)
AO Cards NI-9264
I am trying to do closed loop control over a load using the loadcell feedback to change the AO on a electromagnetic regulator. The system works fine as a develop piece of code. Once I build it and deploy to the cRIO I do not seem to be able to get to the AI info. I can set up and write to the AO on the same FPGA. I see the load as long as I am not in the RT environment. I have tried using every method I know to get the info. I have used action engines (global funtional variables), Queues, and reading from the FPGA directly. I am not getting the load reading from the FPGA no matter what I try. Anyone seen this before?
Solved! Go to Solution.
My suspicion is that your Open FPGA VI Reference is not configured properly for deployment.
Try remote debugging the startup executable and see if there is any error thrown.
Well I am able to set the AO in the FPGA. I would think if the reference was not configured correctly I would get no response from the FPGA. Is that not correct? I will look through the document links you sent and see if I can use that to help.
Just a quick comment - with the NI-9202 you have to issue a "Start" command to get it to start acquiring data.
There could be plenty of more general reasons why FPGA acquisition loops and its communication to RT might give results that don't appear right. For important to make sure the FPGA code starts up (initialisation > control loop) and RT starts up (initialisation > monitoring loop) in a way that is consistent for both, and quite easy to get messed up if you miss something out. The example VIs are helpful to show how it should be.
OK you didn't read my post. I was able to get this to work in a development environment. If I were not issuing a start then it would not work in the development environment.
I am pretty sure that I figured out the problem. The sampling must happen differently when the code is complied to a startup file. I played around with it for a while. and finally got the system to respond . It had a significant delay. This lead me to believe I had a buffer problem. I adjusted my read loop to look for more FIFO elements after my first read. If there where more waiting I would read again immediately. This seemed to get rid of the delay. I am able to see my load and control it now.