Logging data on Host + Low level + High level control with compactRIO

[ccvalerio]

Hi,

We have available here a cRIO 9075 and I would like to know if it is possible to use it (if not, any other cRIO or even PXI) for rapid prototyping of controllers and logging data do disk (large amount of data, much more than the available space in the cRIO disk, so it should be connected to a host computer with plenty of space in the HD).

There is a low level controller that should have a loop rate of around 100kHz, and the other controllers are not so demanding, in the order of 50Hz.

This same hardware is expected to log some data, like encoder (position + speed), some analog and digital signals at a rate of around 1kHz.

The data acquisition runs will run for around 1-2 hours...

In summary, do you think only writing a FPGA, RT and Host VIs is enough for this task? The high speed controller will be implemented in the FPGA, the others I think that can be done in RT... Am I right?

The data logging can be done this way, from the FPGA -> DMA -> RT -> Ethernet -> Host (desktop computer) at this data rate?

Thanks!

[Abel_Souza]

Hi ccvalerio,

You can create only one FPGA, RT and host VIs for your application, or work with subVIs. If you decide work with subVIs you will need have one main VI for FPGA, one for RT and one for host.

If I understand your encoder data will be acquire at 1kHZ, you will not have problems with it, but like disk access and network communication are not deterministics tasks is important you do these tasks at separated loops.

In summary, you can do your application like you imagine.

Regards,

[ccvalerio]

My only concern was regarding the host, as it is a workstation running windows.

It is not acceptable losing data. It should be all there with a difference between each of the data points of 1ms.

I understand that the network and writing to the disk is not deterministic, but if I use a data streamming / buffered communication mechanism between the RT and the Host I should be able to get a very good file at the end of the test, right? The loop that is acquiring the data is in the FPGA / RT so it should not have a considerable jitter...

Did I understand correctly?

[Abel_Souza]

Yes, with data streaming you will not lose data.

[ccvalerio]

Thank you.

Do you think this same system is suited for hardware in the loop simulations?

[Abel_Souza]

I am not specialized in Hardware-in-the-loop, but I think yes.