High Throughput Divide

[ntmkd]

Deal all, 

I'm developing a FPGA VI to calculate least mean square over 19 samples acquired with NI 9223 I/O module on cRIO-9012 controller and chassis cRIO-9118. You can see my code in the LMS snipped attachment.

I have problems with understanding the Throughput parameter at the Execution Mode section for the configuration of the High Throughput Divide function inside a SCTL. When I set this variable to 1 cycle/sample, it seems to me that the correct results after the high throughput division function are coming after the latency of the function. So for example in this case after 30 cycles. But when I set to the maximum possible value, in this case 29 cycles/sample, I never get correct result of the division, and the result is always increasing until some maximum number, than goes to zero and start increasing in the same manner. So I can't really understand this function.

Can someone please give me more information about the High Throughput Divide function? At least more info about the Throughput parameter.

Thank you very much.

Kind Regards,

Nikola

[ntmkd]

Also I've just check, the Output Valid always gives me FALSE value. The behaviour is very strange, or I'm missing something 🙂

[ntmkd]

Also now I figured out, that even though the expected value of the high throughput divide inside the SCTL is not correct, all other values afterwards, that actually depend on this value are still correct. Very strange behavior 🙂

Hope someone have more experience with this throughput math functions.

Cheers,

Nikola

[reschri · Accepted solution]

Hi Nikola,

You need 30 cycles to get a valid result - regardless what throughput is set. When you set the control to 1 Value/cycle you can feed a value every cycle. The calculation is pipelined and intermediate results are stored in shift registers.

When you set 30cycles/value, only every 30 cycles you can feed a new value. The advantage is, it costs less ressources as fewer piplines are needed.

I think the output valid is not false all the time, it is true once every 30 cycles and you miss it perhaps by watching the VI front panel. use the "output valid" "ready for input" to control the feeding/reading of new values. Otherwise, you can use 1cycle per value if you have the ressources left on the chip,

Regards,

René

[ntmkd]

Hello Ren,

thank you very much for your answer.

I've created a test program to figure it out how is the function working and I clear my doubts. It is working exactly as you are saying. Thank you very much anyway, and sorry for not replying to my thread to let everyone know that I've sloved my problem 🙂

Kind regards,

Nikola

[JCC_(SK)]

There was example or white paper somewhere on ni.com, I found only this:

Scheduling Timing Using Handshaking Signals