FPGA Sample Rate

[Gravy_Train]

I am developing a proof of concept application in LV 8.5.1 that uses the cRIO-9012 Real-Time Consoler with a 4 slot 1M FPGA chassis and I am having problems setting the scan period on the FPGA.  I have attached an image of my FPGA block diagram and my RT application block diagram so I don't have to go through a detailed verbal description of my code.  My problem lies in that my FPGA scan rate will not go any faster than 3Hz.  I set the loop timer ms count on the FPGA from the RT application and then I tell the FPGA to start executing the DAQ loop by "Arming the DAQ".  During the DAQ loop, if I set the Count(mSec) to less than 333 mS my Period Overrun indicator reports back that the loop rate is not keeping up with the prescribed period.  In my RT application I am monitoring if there is a DMA overflow and how many elements are remaining in the DMA buffer, both are indicating that the FPGA loop and the RT loop are running synchronously when I had though I had programmed the FPGA loop to run as fast as it needs to maintain the "sample rate". I know this because the RT application reports there are 0 elements remaining in the DMA buffer.

I have a feeling that the problem may stem from the fact that I am running the RT application through a remote front panel.  I am doing this because this application is a proof of concept and I wanted to avoid having to spend too much time writing an FPGA application, an RT application and a Host application.  Is the fact that the RT front panel has to update remotely some how causing the FPGA vi to execute differently.

I have been trying to follow the plentiful examples from NI, but I cannot seem to find any reason for the slow loop execution on the FPGA.

[Stephen_Moore · Accepted solution]

Hi,

I think that you have got a problem with the type of modules that you are using.  Mod4 would appear to be a 9211 module, given that you have the channels as TC with a CJC and an autozero.  The 9211 is a 24bit delta-sigma module and has a slow conversion time.

Conversion time................................70 ms per channel; 420 ms total for all channels including the autozero and cold-junction channels

FPGA loops can ONLY run as fast as any I/O within them operates.  In your case the 9211 module has a conversion time of70ms per channel and the manual states that the module will take 420 ms for all the channels (4 off TC,CJC & autozero).  I am slightly surpised that you can get the loop to run at 333ms.  If you do need to have faster loop rates then you will need to split your I/O into different loops. 

If you need a faster themocouple reading then you will have to consider using a different module to measure the mV and do the conversions yourself, or consider using RTDs and a 9217 which has a high-resolution mode and a high-speed mode.

Conversion time

High-resolution mode................. 200 ms per channel; 800 ms total for all channels: 

High-speed mode........................2.5 ms per channel; 10 ms total for all channels

Cheers

Stephen

[Gravy_Train]

Thanks for the help Stephen.  I knew about the sample rate limitations of the 9211.  I guess I had made an assumption about the "mechanics" of sampling the 9211 that I should not have.  I assumed that if I read any specific channel on the 9211 faster than it could physically update from the ADC, it would simply report back its last know good reading.  That not being the case, I reprogrammed my application to have a high speed sample loop and a low speed sample loop.

Thanks

Eric