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Communication between simulink model and cRIO-9035 is poor

Hi,

I am trying to run a closed loop control strategy where the simulink model is trying to simulate the motor and my ECU is trying to control the motor. The model provides the hall values to the FPGA for which I have done mappings. I am using a cRIO-9035 as a custom device and UDV's to communicate with the model. My FPGA runs at 300ns and my model step time duration is 50us which is fast enough. The model sends the hall values to FPGA which toggles every 500us but the FPGA is receiving at every 2ms which is quite slow. Is there a reason for this issue or is this a limitation of Veristand? Can anyone help me fix this? 

Thanks and regards

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I've not really used Veristand and Simulink to target a RT cRIO before - so I expect you know a lot more than me:

  • Are you using Veristand to run the model on the RT part of the cRIO ? If so that may limit the fastest achievable sample time. If you need 50usec you may need to get the model runing on the FPGA, but that may not be possible via Veristand and the Mathworks tools (Simulink Coder / Real time workshop). I woudl have thought that there should be something that gives a warning if you try to do something the hardware is not possible.
  • Have you tried simplfying the model, I think some Simulink blocks won't translate, but I wonder if some could be getting translated into quite complex functions that can work on a real-time operating system. With that in mind, have you checked the cRIO CPU loading.

Good luck

Consultant Control Engineer
www-isc-ltd.com
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We've had success using the Model Interface Toolkit to run a Simulink model on RT. The model is executed in a timed loop in the Real-Time OS with a loop rate of 20kHz (50µs period). Some of the inputs for the model are read from multiple FPGA targets, and the outputs of the model are written back to the FPGAs as well. 

 

The limiting factor in our case was communication with the FPGA targets.


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That's what I feel the the communication using User-Defined Variables is slow. My model is running on RT at a fast rate and in Veristand I can see that the time step duration is around 50us which is correct, but the values that I receive in FPGA is slow and every 2ms. while my FPGA is running at 300ns.

Is there a way to improve the communication between UDV's and FPGA? or is it not possible as there is a hard limit?

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