I'm currently using a PXIe-8133 in a 1062 to read from a PXI-7842 RIO card. I currently have a large FIFO set up with the 'FPGA-to-Host DMA' configuration. When I add this into my core loop on my RT system, I notice it increases the average execution time of the loop by around 8uS. I'm curious now, if I want to read only 6 digital inputs from the FPGA into this data aquisition loop, what's the quickest way to do it? Am I better off using the digital inputs of say a PXIe-6363?

Real-Time Measurement and Control

CVI RT read from FPGA DMA FIFO Speeds

Just out of curiosity, have you tried implementing the read by just polling an indicator from the FPGA rather than DMA'ing it? If you only need the most recent value, it doesn't make sense to construct a DMA, and that should reduce your read time.

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Yes, but I'm not sure what mechanism it uses to read/write to those indicators. Doesn't that use DMA as well?

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Real-Time Measurement and Control

CVI RT read from FPGA DMA FIFO Speeds

Re: CVI RT read from FPGA DMA FIFO Speeds

Re: CVI RT read from FPGA DMA FIFO Speeds