Arbitration and shared resources (FPGA)

[St3ve]

Hi,

I'm looking for a way of sharing a number of boolean flags between VIs on FPGA in a Current Value Table manner. In general these flags have one writer and many readers. The writer may be a 'real' boolean from a digital input module or it may be an internally derrived flag.

An obvious way to do this is using a single global for all of the flags. However, the arbitration settings for globals and non-reentrant VIs are fixed and I don't know what the behaviour will be in this case.

I assume that as Globals are in FPGA gates, not RAM there is no need for arbritration for multiple readers. I assume this as it becomes a 'hardwire wire' with one source and multiple destinations on the FPGA - like with locals (multiple readers of FPGA front panel controls).

Is this correct? If not does anyone have any examples of how to structure inter-process, CVT, communication on FPGA?

Thanks,

Steve.

[MikeParkin]

Hi Steve,

I believe you are correct. However, it might be worth adding some code which does acts if there is a conflict due to simultaneous entrants.

You can only change the arbitration options on IO and FIFO's. If you can ensure that multiple accessors don't occur at the same time then arbitration shouldn't be an issue.

The following link might be of interest to you:  http://zone.ni.com/reference/en-XX/help/371599B-01/lvfpgaconcepts/fpgaarbintro/