IF-RIO--Compilation error

[sree_405]

Hi Sir.Madam,

This is Sreenivasulu.I generated some digital modulated signal LabVIEW 8.2 and NI 5640R card.

after one month i come back to LabVIEW work.now i am unable to compile the FPGA VI.i am getting this proble.

Summary:Status: Compilation failed.

Refer to the advanced tab for more information, or contact National Instruments technical support at ni.com/support.

Start Time: 8/28/2008 6:31:45 PM
End Time: 8/28/2008 6:34:42 PM

Advanced:Release 8.1.03i - Xilinx CORE Generator IP_I.20
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Regenerating IP...
occurred during initialization of Vnot reserve enough space for object heanot create the Java virtual machineERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
Regenerating IP...
occurred during initialization of Vnot reserve enough space for object heanot create the Java virtual machineERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.

I am unable to find the problem.Previously i compiled very well.now i am following same procedure.

Please tell me where the problem.

Thanking you sir.

Sreenivasulu.O

cell:09394822850

[sree_405]

Hi This Sreenivasulu  agian.

i am able to compile one example project(ni5640R Single Tone Output.zip).

i am unable to  compilethis project(ni5640R IQ Output.zip).

Here i am attaching these two project.

Regards

Sreenivasulu.O

[Vinay_Kumar]

Hi Sree,

I tried compiling the same project in LV 8.2.1, and i did not get the error that you have reported

"Release 8.1.03i - Xilinx CORE Generator IP_I.20
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Regenerating IP...
Generating Implementation files.
Generating the VHDL instantiation template.
Generating VHDL structural model.
Finished Regenerating.
Successfully generated core_prim_eq_0061equnsigned16.
Regenerating IP...
Generating Implementation files.
Generating the VHDL instantiation template.
Generating VHDL structural model.
Finished Regenerating.
Successfully generated core_prim_eq_0062equnsigned16."

Please do look at http://www.xilinx.com/support/answers/21955.htm

Since you had compiled the project successfully previously, i do not know why you are seeing this error now.

However, i waited for the compilation to get over but failed after HDL compilation.

If you have LV 8.5, can you try compiling in lv8.5?

The project compiles fine on my machine in lv8.5.

[JerryAL]

Hi Sreenivasulu

I suspect an isolated problem on your computer.  I don’t know any more than what is on the XILINX site at the link that Vinay provided.

I compiled both your files with no issues here.

I suggest that you uninstall the Xilinx component under National Instruments in "Add and Remove Software" and the reinstall Xilinx again.

There two ways to remove Xilinx

(1) Go to National Instruments under Add/Remove Program and select to remove "Compile Server"

(2) Run the installer  and uncheck Xilinx Component.

To reinstall Xilinx, run the LabVIEW FPGA installer again and check the Xilinx Component

Jerry