trigger multi chassis

[pulsed_power]

I am adding a PXIe chassis with three FlexRIO FPGAs and digitzer adapter modules to an existing PXI chassis with timing and Multifunction DAQ cards.

In this question I would like to focus on triggering all cards in the PXI and PXIe systems at the same time. For now I would like to ignore that fact that ideally all clocks of should be synchronized and am willing to have sampling time uncertainties on the order of one clock cycle between the different cards. 

My plan is as follows I intialize NI-Sync on the master and slave timing and synchronization module of the respective chassis. I connect software triggers to the PXI star lines of the master chassis and to a PFI line of the master syncrhonization card. Then I connect a PFI line of the slave chassis to the PXI star lines. In addition I connect the PXI clocks. Finally I trigger the software trigger. 

I attached an image of the setup from NI MAX and a sample NI-sync VI going through the trigger line setup.

 

I have several questions:

Are there any references on multichassis triggering? I found the NI sync examples in LabVIEW and Getting started with Multichassis Synchronization useing the NI PXI-6653 and the NI PXI-4472.

Is the block diagram of the attached VI appropriate? Why do I get error 1074118586 "A resource necessary to complete the specified operation is not available; therefore, the operation cannot be completed" when I try to connect more than 3 PXI star lines with a PFI line?

What wiring is needed between the Timing and Synchronization modules for the attached code? It seems like Clock Out and Clock In of each module need to be connected and a PFI line to enable the triggering need to be connected. However, the pictures in the Timing Synchronization modules specsheets and the Getting started with Multichassis Synchronization useing the NI PXI-6653 and the NI PXI-4472 seem to indicate that 2 PFI lines must be connected between the modules and the master module must have a coax cable from one of its PFI lines to another on the same module.

Thank you!

[thebatmanboy]

In regards to -1074118586: it sounds like you may need to reserve the reserving the segment of the bus in MAX:

http://digital.ni.com/public.nsf/allkb/3DBF4244013C4310862578AE007036F0

[JamesB.]

thebatmanboy's response is related to PXI_Trig, but your code is using PXI_Star. You should not need to manually reserve any segments in MAX for this prototype (even after implementing the changes I suggest below).

The multichassis reference guide you linked to is actually pretty thorough; I'm not aware of a better reference.

You get error -1074118586 because you are trying to route to PXI_Star lines that do not exist in your 1042Q chassis. That chassis has 8 slots: 1 controller, 1 system timing slot, and 6 peripheral slots. Only PXI_Star0-5 are valid. Were you trying to use PXI_Trig? PXI_Trig lines would be better for sharing the sync pulse and start trigger described in the reference document; PXI_Star is better for sharing the sample clock.

The VI as you've written it isn't accounting for the additional propagation delay from one chassis to the other. Here's what I would do: use the 6653 as your timing master (it has a better oscillator than the 6672). Route the software trigger to 6653/PFI0 and 6653/PFI1. Use one cable to connect 6653/PFI1 to 6653/PFI5 (wrapping the signal back to the same card), and route PFI5 to a single PXI_Trig line in the 1042Q chassis. Use another cable of the same length to connect 6653/PFI0 to 6672/PFI2, and route PFI2 to a single PXI_Trig line in the 1082 chassis. When you activate the software trigger, it should arrive at both backplanes with very low skew. But devices will not trigger at the same time because of the propagation delay through each backplane; devices closer to the system timing slot in each chassis will receive the trigger earlier than devices farther away. Solving that problem will require more sophisticated triggering and clock sharing. The section of the reference guide you linked titled "Using the NI 6653 to Route Synchronization Signals Between Multiple Chassis," starting on page 9, walks you through a lot of the concepts (even though you don't have a 4472 in your system).

Good luck, and I'll try to watch this thread for updates.

(P.S. I chose specific PFI lines arbitrarily with a goal of clarity. Any available PFI line should work.)

[pulsed_power]

Thank you James.

I think your comments cleared some things up for me. I am currently also working on codeing the FPGAs we will be using in the new chassis. This week I am working on the FPGAs. I will get back to the triggering and post a reply by the end of next week.