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SERDES CLIP in External clock data Acquisition in Flex RIO

Can anyone explain the detailed structure of an SERDES Connector CLIP

in LabVIEW programming Flex RIO.

 

Additionally,

  1. How do the acquisition bits get arranged, with respect to each Channel Data?!
  2. How does the samples to be read considered?!!!
  3. If I have 16 LVDS Channels, how can I acquire each channels data considering each Lane to reconstruct separately.

Note: 

I have seen examples and stuffs related to flex-rio programming but there's no particular explanation for this CLIP, Where things go in deep with high importance.

 

KT is worth it!! Cause you are storing things permanently in your Brain Smiley Wink

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Message 1 of 10
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Which FlexRIO and FlexRIO Adapter Module are you using? 


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Message 2 of 10
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Flex RIO series is PXI7966 and

Adapter module is PXI6587

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Message 3 of 10
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Hello everyone,

 

Please help me with sorting out this problem!! Smiley Frustrated

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Message 4 of 10
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Have you reviewed: http://zone.ni.com/reference/en-XX/help/372614J-01/friohsdio/6587_serdesconn_clipref/

Have you reviewed the Properties of the IO Module?

Right click on IO Module >> Properties, select 6587 and on the right is a list of CLIP options:

 

6587.png

 

 


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Message 5 of 10
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Hey,

 

I have already read these documents and am not getting a proper idea.

In my application, the data lanes 6 to 9 are used. From which the data 

is read and re-constructed for a sine wave. But, am not getting the Sine

wave. So, what I doubt now is the CLIP and in which order it sends the 

data..

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Message 6 of 10
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So you are unable to get the example to work?

Maybe simplify what you are trying to do?  Otherwise, I would suggest reaching out to (phone) NI technical support.

 


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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@Terry_ALE wrote:

So you are unable to get the example to work? 


Am able to make the example code work, Terr_ALE

 

The changes in my application, what am trying is to let a clock signal and data line, sample data with respect to the clock signal, in DDR mode. And then reconstruct, through Digital to Analog function. 

Am not able to understand how to get, the detection of rising and falling edges of a clock without connecting it to Clock IN pin on the Adapter module (Cause, Signals are LVDS) or as reference.

 

 

Is this detail..?!

 

Thanks!!

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Message 8 of 10
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I think NI technical support (phone/email) is your best route at this point.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Message 9 of 10
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Hi PriyadarsiniS

Do you still have questions about the SERDES CLIP or w
ere you able to create a service request to get the information you were looking for? 
The documentation that Terry_Ale provided is a great place to start to understand the SERDES CLIP but if you have more questions related to your specific application, especially when modifying example code, a service request will be a better route. 

Shalini M.
Partner Development Engineer
Alliance Partner Network
National Instruments
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