PXI support FPGA In Parallel

[Bigbigbang~~~]

Hi all，Do you  know A PXI chassis supports a maximum of several FPGA boards running in parallel, that is to say, there is a controller(PXIe-8881) as the master node deployment simulink controller model, n FPGA(PXIe-7868) as the slave node deployment circuit model, how is the signal bandwidth distribution of their self-check, how to calculate the delay caused?

[ZYOng]

It depends on how the data are being sent and received between different FPGA targets. When you use Open FPGA VI Ref and read/write via either FIFO or I/O Node, the data are processed and pass thru the controller. The lowest latency is implemented using Peer-to-Peer Streaming. The model of the chassis and the location of the module in the chassis have an impact on the bandwidth.

[santo_13]

So far PXIe-1095 seems to be the best with 24GB/s throughput (even across other PXI manufacturers)

[Terry_ALE]

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@ZYOng wrote:

It depends on how the data are being sent and received between different FPGA targets. When you use Open FPGA VI Ref and read/write via either FIFO or I/O Node, the data are processed and pass thru the controller. The lowest latency is implemented using Peer-to-Peer Streaming. The model of the chassis and the location of the module in the chassis have an impact on the bandwidth.

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In addition some cards have multi-gigabit transceivers (MGT) which allow for direct communications between NI FPGA cards.

[Bigbigbang~~~]

Thanks，that's very help！